Phase locked loop and method for adjusting the frequency and phase in the phase locked loop
AssigneeInternational Business Machines Corporation
InventorsMarcel A. Kossel, Thomas E. Morf, Martin L. Schmatz, Silvan Wehrli
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Abstract
A phase locked loop (PLL) which includes a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and generating a digital value representing the phase difference between the reference signal and the oscillator signal. The PLL further includes a state machine for phase acquisition that is capable of generating a control value depending on the digital value, and a controllable oscillator that is capable of generating the oscillator signal depending on the control value.
Claims9
Phase locked loop comprising:
- a phase frequency detector coupled with a time to digital converter capable of comparing a reference signal with an oscillator signal and of generating a digital value representing the phase difference between the reference signal and the oscillator signal;
- a state machine for phase acquisition capable of generating a control value depending on the digital value;
- and
- a controllable oscillator capable of generating the oscillator signal depending on the control value;
- wherein the time to digital converter comprises a delay line with several delay elements that can be sampled by a sampling clock;
- and
- wherein the sampling clock is gained from a conjunction of the outputs of the phase frequency detector.
Dependencies are inferred from the claim text.