Test clock generating apparatus
AssigneeRealtek Semiconductor Corp.
InventorsTa-Chia Yeh, Chien-Kuang Lin, Chi-Feng Wu
Life of this patent
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Abstract
A test clock generating apparatus is provided in the invention. The test clock generating apparatus includes an at-speed clock generator and a multiplexer. The at-speed clock generator is for receiving a reference clock signal and a scan chain enable signal and outputting an at-speed clock signal. The frequency of the at-speed clock signal is substantially the same with that of the reference clock signal. The multiplexer is for receiving the at-speed clock signal and a scan chain clock signal and outputting a test clock signal according to the scan chain enable signal. The frequency of the reference clock signal is higher than that of the scan chain clock.
Claims20
An apparatus for generating a test clock signal in a chip, the apparatus comprising:
- a first clock generator, for outputting a first clock signal, wherein the first clock generator comprises:
- at least one flip-flop, for receiving a reference clock signal and outputting a synchronized signal according to a scan chain enable signal;
- and
- a pulse controller, coupled to the at least one flip-flop, for controlling a pulse number of the reference clock signal according to the synchronized signal and accordingly outputting the first clock signal;
- and
- a multiplexer, for receiving the first clock signal, a scan chain clock, and selecting one of the first clock signal and the scan chain clock to output the test clock signal according to the scan chain enable signal;
- wherein the frequency of the first clock signal is higher than that of the scan chain clock.
A method of generating a test clock signal for testing a chip, the method comprising:
- generating a synchronized signal according to a reference clock signal and a scan chain enable signal;
- controlling a pulse number of the reference clock signal according to the synchronized signal and accordingly generating an internal clock signal;
- receiving a scan chain clock;
- and
- outputting the test clock signal according to the scan chain enable signal;
- wherein the test clock signal comprises components of the internal clock signal and the scan chain clock.
An apparatus for generating a test clock signal in a chip, the apparatus comprising:
- an input terminal, for receiving a scan chain clock;
- and
- a test clock generator, coupled to the input terminal, for receiving the scan chain clock, generating a synchronized signal according to a reference clock signal and a scan chain enable signal, controlling a pulse number of the reference clock signal according to the synchronized signal to produce a first output clock, and selecting one of the first output clock and the scan chain clock to output the test clock signal comprising a first frequency and a second frequency;
- wherein when the apparatus is in a normal mode, the first frequency of the test clock signal and an operational frequency of the chip are substantial the same;
- and when the apparatus is in a shift mode, the second frequency of the test clock signal and that of the scan chain clock are substantial the same.
Dependencies are inferred from the claim text.