Delay apparatus and method thereof
AssigneeVIA Technologies, Inc.
InventorsJingran Qu, Zhongding Liu, Chun-Fu Lin
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Abstract
The present invention provides a delay apparatus for delaying an input signal by a predetermined delay amount, including: a plurality of delay units for respectively delaying the input signal by the predetermined delay amount, each delay unit having a plurality of delay cells for respectively delaying the input signal by a certain delay period; and a sub decoding unit for generating a plurality of sub control signals to each of the delay units according to a first control signal and a selecting signal, wherein only delay cell of all the delay units is outputted at a time according to the sub controls signals.
Claims19
A delay apparatus for delaying an input signal with a predetermined delay amount, comprising:
- a plurality of delay cells connected in series for successively delaying the input signal with the predetermined delay amount according to a sub control signal provided to each delay cells, wherein each delay cell respectively has a delay period;
- a sub decoding unit coupled to the delay cells for generating the sub control signal according to a first control signal and a selecting signal;
- and a decoding unit coupled to the sub decoding unit for generating the first control signal and the selecting signal according to a counting value;
- wherein only one of the delay cell is outputted at a time;
- and
- wherein, one of the delay cells is used to fine tune the input signal according to a second control signal generated by the decoding unit according to the counting value.
A delay apparatus for delaying an input signal as an output signal with a predetermined delay amount, comprising:
- a decoding circuit for generating a first control signal and a selecting signal according to a counting value, and further generating a plurality of sub control signals according to the first control signal and the selecting signal;
- and
- a plurality of delay units connected in series for successively delaying the input signal, wherein each of the delay units respectively delays the input signal for the predetermined delay amount according to one of the sub control signals;
- wherein only one of the sub control signals is valid and only one bit of the valid sub control signal is enabled at a time.
Dependencies are inferred from the claim text.