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US 7,403,055 B2Granted
Duty cycle detector with first and second oscillating signals
AssigneeInfineon Technologies AG
InventorAlessandro Minzoni
Life of this patent
Estimating the term…
Abstract
A duty cycle detector including a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a clock signal having a first duty cycle and to provide a first oscillating signal having a first period proportional to the first duty cycle. The second circuit is configured to receive an inverted clock signal that is the inverse of the clock signal and having a second duty cycle and to provide a second oscillating signal having a second period proportional to the second duty cycle. The third circuit is configured to provide first output signals that indicate the first duty cycle of the clock signal based on a first phase difference between the first oscillating signal and the second oscillating signal.
Claims33
An integrated circuit, comprising:
- a first circuit configured to receive a clock signal having a first duty cycle and to provide a first oscillating signal having a first period that is adjusted based on the first duty cycle;
- a second circuit configured to receive an inverted clock signal that is the inverse of the clock signal and having a second duty cycle and to provide a second oscillating signal having a second period that is adjusted based on the second duty cycle;
- and
- a third circuit configured to provide first output signals that indicate the first duty cycle of the clock signal based on a first phase difference between the first oscillating signal and the second oscillating signal.
1 more element
An integrated circuit, comprising:
- a first circuit configured to receive a clock signal having a first duty cycle and to provide a first oscillating signal having a first period proportional to the first duty cycle;
- a second circuit configured to receive an inverted clock signal that is the inverse of the clock signal and having a second duty cycle and to provide a second oscillating signal having a second period proportional to the second duty cycle;
- and
- a third circuit configured to provide first output signals that indicate the first duty cycle of the clock signal based on a first phase difference between the first oscillating signal and the second oscillating signal, wherein the first circuit is configured to receive an enable signal and provide the first oscillating signal in response to an active enable signal and the second circuit is configured to receive the enable signal and provide the second oscillating signal in response to the active enable signal.
1 more element
An integrated circuit, comprising:
- a first ring oscillator configured to provide a first periodic signal;
- a first delay circuit configured to receive a clock signal having a first duty cycle and provide first delays in the first ring oscillator based on the first duty cycle;
- a second ring oscillator configured to provide a second periodic signal;
- a second delay circuit configured to receive an inverted clock signal that is the inverse of the clock signal and having a second duty cycle and provide second delays in the second ring oscillator based on the second duty cycle;
- and
- a phase detector configured to provide output signals that indicate one of the first duty cycle is greater than fifty percent and the first duty cycle is less than fifty percent based on a phase difference between the first periodic signal and the second periodic signal.
3 more elements
An integrated circuit, comprising:
- a first ring oscillator including first inverters having a first inverter signal path configured to provide a first periodic signal;
- a first delay circuit configured to receive a clock signal having a first duty cycle and including first capacitors configured to be switched into the first inverter signal path via the clock signal to provide first delays in the first inverter signal path based on the first duty cycle;
- a second ring oscillator including second inverters having a second inverter signal path configured to provide a second periodic signal;
- a second delay circuit configured to receive an inverted clock signal that is the inverse of the clock signal and having a second duty cycle and including second capacitors configured to be switched into the second inverter signal path via the inverted clock signal to provide second delays in the second inverter signal path based on the second duty cycle;
- and
- a first phase detector configured to provide first output signals that indicate one of the first duty cycle is greater than fifty percent and the first duty cycle is less than fifty percent based on a first phase difference between the first periodic signal and the second periodic signal, wherein the first ring oscillator is configured to receive a first enable signal that is active at one of a rising edge and a falling edge of the clock signal and provide the first periodic signal in response to the active first enable signal and the second ring oscillator is configured to receive the first enable signal and provide the second periodic signal in response to the active first enable signal.
3 more elements
An integrated circuit, comprising:
- means for receiving a clock signal having a first duty cycle;
- means for adjusting a first period of a first oscillating signal based on the first duty cycle;
- means for receiving an inverted clock signal that is the inverse of the clock signal and has a second duty cycle;
- means for adjusting a second period of a second oscillating signal based on the second duty cycle;
- and
- means for indicating the first duty cycle in first output signals based on a first phase difference between the first oscillating signal and the second oscillating signal.
3 more elements
An integrated circuit, comprising:
- means for receiving a clock signal having a first duty cycle;
- means for proportioning a first period of a first oscillating signal to the first duty cycle;
- means for receiving an inverted clock signal that is the inverse of the clock signal and has a second duty cycle;
- means for proportioning a second period of a second oscillating signal to the second duty cycle;
- means for indicating the first duty cycle in first output signals based on a first phase difference between the first oscillating signal and the second oscillating signal;
- means for proportioning a third period of a third oscillating signal to the first duty cycle;
- means for proportioning a fourth period of a fourth oscillating signal to the second duty cycle;
- means for indicating the first duty cycle in second output signals based on a second phase difference between the third oscillating signal and the fourth oscillating signal;
- and
- means for indicating the first duty cycle based on the first output signals and the second output signals.
7 more elements
A method of operating an integrated circuit, comprising:
- receiving a clock signal having a first duty cycle;
- adjusting a first period of a first oscillating signal based on the first duty cycle;
- receiving an inverted clock signal that is the inverse of the clock signal and has a second duty cycle;
- adjusting a second period of a second oscillating signal based on the second duty cycle;
- and
- indicating the first duty cycle in first output signals based on a first phase difference between the first oscillating signal and the second oscillating signal.
3 more elements
A method of operating an integrated circuit, comprising:
- receiving a clock signal having a first duty cycle;
- proportioning a first period of a first oscillating signal to the first duty cycle;
- receiving an inverted clock signal that is the inverse of the clock signal and has a second duty cycle;
- proportioning a second period of a second oscillating signal to the second duty cycle;
- indicating the first duty cycle in first output signals based on a first phase difference between the first oscillating signal and the second oscillating signal;
- proportioning a third period of a third oscillating signal to the first duty cycle;
- proportioning a fourth period of a fourth oscillating signal to the second duty cycle;
- indicating the first duty cycle in second output signals based on a second phase difference between the third oscillating signal and the fourth oscillating signal;
- and
- indicating the first duty cycle based on the first output signals and the second output signals.
7 more elements
A method of operating an integrated circuit, comprising:
- providing a first periodic signal via a first ring oscillator;
- receiving a clock signal having a first duty cycle;
- switching first delays into the first ring oscillator based on the first duty cycle;
- providing a second periodic signal via a second ring oscillator;
- receiving an inverted clock signal that is the inverse of the clock signal and having a second duty cycle;
- switching second delays into the second ring oscillator based on the second duty cycle;
- and
- indicating one of the first duty cycle is greater than fifty percent and the first duty cycle is less than fifty percent based on a phase difference between the first periodic signal and the second periodic signal.
5 more elements
A method of operating an integrated circuit, comprising:
- providing a first periodic signal via first inverters having a first inverter signal path configured to provide the first periodic signal;
- receiving a clock signal having a first duty cycle;
- switching first capacitors into the first inverter signal path via the clock signal to provide first delays in the first inverter signal path based on the first duty cycle;
- providing a second periodic signal via second inverters having a second inverter signal path configured to provide the second periodic signal;
- receiving an inverted clock signal that is the inverse of the clock signal and having a second duty cycle;
- switching second capacitors into the second inverter signal path via the inverted clock signal to provide second delays in the second inverter signal path based on the second duty cycle;
- receiving a first enable signal that is active at one of a rising edge and a falling edge of the clock signal;
- providing the first periodic signal and the second periodic signal in response to the active first enable signal;
- and
- indicating in first output signal one of the first duty cycle is greater than fifty percent and the first duty cycle is less than fifty percent based on a first phase difference between the first periodic signal and the second periodic signal.
7 more elements
Dependencies are inferred from the claim text.