Flip-flop, integrated circuit, and flip-flop resetting method
AssigneeFujitsu Limited
InventorMakoto Mori
Life of this patent
Estimating the term…
Abstract
A flip-flop which eliminates a reset wiring to prevent complication of a wiring in an LSI or to increase the number of channels used for a signal wiring, an integrated circuit using the same, and a flip-flop resetting method, are provided. The flip-flop performing a reset operation by detecting a change in a power supply voltage includes a state retaining node that stores a HIGH level voltage or a LOW level voltage, and a reset signal generation circuit that detects a change in a power supply voltage exceeding a predetermined value to generate a reset signal for resetting a data storing state of the state retaining node.
Claims4
An integrated circuit having a flip-flop, wherein
- the flip-flop comprising:
- a state retaining node that stores a HIGH level voltage or a LOW level voltage;
- and
- a reset signal generation circuit that detects a change in a power supply voltage exceeding a predetermined value to generate a reset signal for resetting a data storing state of the state retaining node
- wherein the flip-flop is provided by a plural number, and the plurality of the flip-flops are divided into a plurality of groups such that different power supply voltages are separately introduced to the respective groups.
An integrated circuit having a flip-flop, wherein
- the flip-flop comprising:
- a state retaining node that stores a HIGH level voltage or a LOW level voltage;
- a reset signal generation circuit that detects a change in a power supply voltage exceeding a predetermined value to generate a reset signal for resetting a data storing state of the state retaining node;
- a power supply circuit capable of changing the power supply voltage;
- and
- a reset logic circuit that changes the power supply voltage output by the power supply circuit in accordance with a signal sent by an operation system or a predetermined hardware.
An integrated circuit having a flip-flop, wherein
- the flip-flop comprising:
- a state retaining node that stores a HIGH level voltage or a LOW level voltage;
- a reset signal generation circuit that detects a change in a power supply voltage exceeding a predetermined value to generate a reset signal for resetting a data storing state of the state retaining node;
- and
- a reset logic circuit that changes the power supply voltage output by the power supply circuit in accordance with a signal sent by an operation system or a predetermined hardware.
Dependencies are inferred from the claim text.