Low-power transceiver architectures for programmable logic integrated circuit devices
AssigneeAltera Corporation
InventorsSergey Shumarayev, Wilson Wong, Tim Tri Hoang, Thungoc M. Tran, Richard G. Cliff
Life of this patent
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Abstract
High-speed serial interface or transceiver circuitry on a programmable logic device integrated circuit (“PLD”) includes features that permit the PLD to satisfy a wide range of possible user needs or applications. This range includes both high-performance applications and applications in which reduced power consumption by the PLD is important. In the latter case, any one or more of various features can be used to help reduce power consumption.
Claims20
A programmable logic device integrated circuit comprising:
- core circuitry;
- and
- high-speed serial interface circuitry, the high-speed serial interface circuitry including:
- physical medium attachment (PMA) circuitry;
- protocol coding sublayer (PCS) circuitry for processing signals in transit between the PMA circuitry and the core circuitry;
- and
- bypass circuitry for selectively allowing signals to pass between the PMA circuitry and the core circuitry without passing through the PCS circuitry.
A programmable logic device integrated circuit comprising:
- core circuitry;
- and
- high-speed serial interface circuitry, the high-speed serial interface circuitry including:
- physical medium attachment (PMA) circuitry including a plurality of analog circuit components;
- protocol coding sublayer (PCS) circuitry for processing signals in transit between the PMA circuitry and the core circuitry;
- input circuitry for receiving a power signal from an external source;
- regulator circuitry for producing a regulated power signal from the power signal;
- and
- routing circuitry associated with at least one of the analog circuit components for selectively applying either the power signal or the regulated power signal to that analog circuit component.
A programmable logic device integrated circuit comprising:
- core circuitry;
- and
- high-speed serial interface circuitry, the high-speed serial interface circuitry including:
- physical medium attachment (PMA) circuitry;
- protocol coding sublayer (PCS) circuitry for processing signals in transit between the PMA circuitry and the core circuitry, and having a clock signal input;
- and
- circuitry for selectively applying either (1) a time-varying clock signal or (2) a substantially constant signal to the clock signal input.
Dependencies are inferred from the claim text.