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US 7,402,914 B2Granted
Semiconductor device featuring overlay-mark used in photolithography process
AssigneeNEC Electronics Corporation
InventorHirofumi Saito
Life of this patent
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Abstract
In a semiconductor device, an insulating layer formed on a substrate and a wiring pattern layer is formed on the insulating layer. A lower mark element is defined as a groove formed in the insulating layer, and defines an overlay mark in conjunction with an upper mask element formed in a photoresist pattern coated on the insulating layer for the formation of the wiring pattern layer. The lower mark element features a width falling within a range from approximately 4 to 6 μm, and a depth of at most 1 μm.
Claims20
A semiconductor device comprising:
- an insulating layer formed on a substrate;
- a wiring pattern layer formed on said insulating layer;
- and
- a lower mark element defined as a groove formed in said insulating layer, said lower mark element defining an overlay mark in conjunction with an upper mask element formed in a photoresist pattern coated on said insulating layer for the formation of said wiring pattern layer,
- wherein said lower mark element features a width falling within a range from approximately 4 to 6 μm, and a depth of at most 1 μm.
2 more elements
A semiconductor device comprising:
- an insulating layer formed on a substrate;
- a lower mark element defined as a groove formed in said insulating layer;
- a metal layer formed on said insulating layer;
- a photoresist pattern formed on said metal layer;
- and
- an upper mark element defined as an opening formed in said photoresist pattern, both said lower mark element and said upper mark element defining an overlay mark in conjunction with each other,
- wherein said lower mark element features a width falling within a range from approximately 4 to 6 μm, and a depth of at most 1 μm.
4 more elements
Dependencies are inferred from the claim text.