Backside contacts for MOS devices
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMong Song Liang, Hun-Jan Tao
Life of this patent
Estimating the term…
Abstract
A semiconductor structure includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a gate dielectric over the first surface of the semiconductor substrate, a gate electrode over the gate dielectric, a source/drain region having at least a portion in the semiconductor substrate, a dielectric layer having a first surface and a second surface opposite the first surface wherein the first surface of the dielectric layer adjoins the second surface of the semiconductor substrate, and a contact plug in the dielectric layer, wherein the contact plug extends from a bottom side of the source/drain region to the second surface of the dielectric layer.
Claims18
A semiconductor structure comprising:
- a semiconductor substrate having a first surface and an opposing second surface;
- a gate dielectric over the first surface of the semiconductor substrate;
- a gate electrode over the gate dielectric;
- a source/drain region having at least a portion in the semiconductor substrate;
- a dielectric layer having a first surface and an opposing second surface, wherein the first surface of the dielectric layer adjoins the second surface of the semiconductor substrate;
- and
- a first contact plug in the dielectric layer, wherein the first contact plug extends from a bottom side of the source/drain region to the second surface of the dielectric layer, and wherein the first contact plug comprises a silicide region adjoining the source/drain region.
A semiconductor structure comprising:
- a semiconductor layer comprising a first side and an opposing second side;
- a buried oxide (BOX) layer directly on a top surface of the second side of the semiconductor layer;
- a gate dielectric over a top surface of the semiconductor layer on the first side;
- a gate electrode over the gate dielectric;
- a source/drain region in the semiconductor layer, wherein the source/drain region and the BOX layer have an interface;
- a first contact plug in the dielectric layer and connected to the interface;
- an over-device metallization layer over and on the first side of the semiconductor layer;
- and
- an under-device metallization layer on the second side of the semiconductor layer, wherein the under-device metallization layer is connected to the first contact plug, and wherein the over-device metallization layer and the under-device metallization layer are electrically interconnected through contact plugs.
A semiconductor structure comprising:
- a semiconductor substrate having a first surface and an opposing second surface;
- a gate dielectric over the first surface of the semiconductor substrate;
- a gate electrode over the gate dielectric;
- a source/drain region having at least a portion in the semiconductor substrate;
- a contact etch stop layer (CESL) over the gate electrode and the source/drain region, wherein the CESL has an inherent stress, and wherein a thickness of the CESL is between about 700 Å and about 2000 Å;
- a dielectric layer having a first surface and an opposing second surface, wherein the first surface of the dielectric layer adjoins the second surface of the semiconductor substrate;
- and
- a first contact plug in the dielectric layer, wherein the first contact plug extends from a bottom side of the source/drain region to the second surface of the dielectric layer.
Dependencies are inferred from the claim text.