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US 7,402,862 B2Granted
Multi-bit non-volatile memory device having a dual-gate and method of manufacturing the same, and method of multi-bit cell operation
AssigneeKorea Advanced Institute of Science and Technology
InventorsYang-Kyu Choi, Hyunjin Lee
Life of this patent
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Abstract
The present invention relates to a multi-bit non-volatile memory device having a dual gate employing local charge trap and method of manufacturing the same, and an operating method for a multi-bit cell operation.
Claims10
A multi-bit non-volatile memory device having a dual gate structure, comprising:
- a silicon substrate;
- a lower insulating film formed over the silicon substrate;
- a silicon layer formed over the lower insulating film and, having a silicon pin at the center of the silicon layer in which a source region and a drain region are formed on both sides of the silicon pin and the silicon pin is formed to have a shape having corners;
- sequentially formed tunneling oxide film, electron trap film and a control oxide film positioned relative to the center of the silicon pin;
- gate material over the control oxide film;
- and
- wherein the source and drain regions are asymmetrically formed in a silicon channel and the silicon pin is formed to have a wider region at the source region than at the drain region.
4 more elements
A method of operating a memory device, comprising:
- in a multi-bit non-volatile memory device having a dual gate structure,
- wherein in a read operation of electrons trapped at the electron trap film, values of threshold voltages between a normal direction read (VD>VS) condition and a reverse direction read (VD>VS) condition are different depending on a location where the electrons are trapped,
- wherein in the case where a read operation is performed on a program in which electrons are trapped at the electron trap film of drain-side silicon pin corners, the reverse direction read (VD>VS) condition having an opposite direction to that of an operating voltage (VD>VS) of the program is employed, and
- in the case where a read operation is performed on a program in which electrons are trapped closer toward the center of the channel and away from the source-side silicon pin corners, the normal direction read (VD>VS) condition having an opposite direction to that of an operating voltage (VD>VS) of the program is employed.
1 more element
Dependencies are inferred from the claim text.