Method, system, and apparatus for reducing transition capacitance
AssigneeSun Microsystems, Inc.
InventorLeesa M. Noujeim
Life of this patent
Estimating the term…
Abstract
A printed circuit board (PCB) is provided. The PCB includes a signal layer, a first reference plane defined adjacent to a first side of the signal layer, and a via passing through the signal layer and the first reference plane. The first side of the signal layer is either above the signal layer or below the signal layer. The via is configured to accept an electrical signal to be routed on the signal layer. The inner area of the first reference plane up to the via is capable of being eliminated.
Claims16
A printed circuit board (PCB) onto which an integrated circuit package containing an integrated circuit is mounted, comprising:
- a signal layer;
- a first reference plane defined adjacent to a first side of the signal layer, the first side of the signal layer being one of above the signal layer and below the signal layer;
- and
- a via passing through the signal layer and the first reference plane, the via in electrical communication with the signal layer,
- wherein an inner area of the first reference plane up to the via is eliminated, and wherein a portion of the first reference plane is disposed below the integrated circuit.
A printed circuit board (PCB) onto which an integrated circuit package containing an integrated circuit is mounted, comprising:
- an upper signal layer;
- a lower signal layer;
- an upper reference plane separating the upper signal layer and the lower signal layer;
- a lower reference plane disposed under the lower signal layer;
- an innermost via configured to accept an electrical signal from an innermost contact terminal to be routed on the upper signal layer;
- and
- an outermost via configured to accept an electrical signal from an outermost contact terminal to be routed on the lower signal layer,
- wherein at least one of an inner area of the upper reference plane up to the innermost via and an inner area of the lower reference plane up to the outermost via are eliminated, and wherein a portion of the upper reference plane and the lower reference plane are disposed below the integrated circuit.
An electronic system, the system comprising:
- a printed circuit board (PCB) onto which an integrated circuit package containing an integrated circuit is mounted, the PCB including,
- an upper signal layer;
- a lower signal layer;
- an upper reference plane separating the upper signal layer and the lower signal layer;
- a lower reference plane disposed under the lower signal layer;
- an innermost via;
- and
- an outermost via;
- and
- a chip component mounted on the PCB, the chip component including a plurality of successive contact terminals, the innermost via is in electrical communication with an innermost contact terminal of the plurality of successive contact terminals to be routed on the upper signal layer and the outermost via is in electrical communication with an outermost contact terminal of the plurality of successive contact terminals to be routed on the lower signal layer,
- wherein at least one of an inner area of the upper reference plane up to the innermost via and an inner area of the lower reference plane up to the outermost via are eliminated, and wherein a portion of the upper reference plane and the lower reference plane are disposed below the integrated circuit.
Dependencies are inferred from the claim text.