Method of incorporating stress into a transistor channel by use of a backside layer
AssigneeTexas Instruments Incorporated
InventorsMahalingam Nandakumar, Haowen Bu
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Abstract
The present invention provides the method includes forming source/drain regions 170 in a semiconductor wafer substrate 110 adjacent a gate structure 130 located on a front side of the semiconductor wafer substrate 110. The source/drain regions 170 have a channel region 175 located between them. A first stress-inducing layer 190 is placed on a backside of the semiconductor wafer substrate 110 and is subjected to a thermal anneal to cause a stress to form in the channel region 175.
Claims20
A method for manufacturing a semiconductor device, comprising:
- forming source/drain regions in a substrate of a semiconductor wafer adjacent a gate structure located on a front side of the semiconductor wafer, the source/drain regions having a channel region located therebetween;
- placing a first stress-inducing layer on a backside of the semiconductor wafer, wherein the first stress-inducing layer is a first layer deposited on the backside of the semiconductor wafer such that the first stress-inducing layer resides only on the backside of the semiconductor wafer;
- subjecting the first stress-inducing layer to a thermal anneal to cause a stress to form in the channel region;
- and
- placing a second stress-inducing layer over the gate and source/drain regions wherein the second stress-inducing layer imparts a tensile stress to channel region.
A method of manufacturing an integrated circuit, comprising:
- forming transistors on and within a substrate of a semiconductor wafer, the transistors including completed gates, wells formed within the substrate and source/drain regions formed in the wells with each of the source/drains regions having a channel region formed therebetween;
- subsequent to forming the transistors, placing a first stress-inducing layer on a backside of the semiconductor wafer;
- placing a second stress-including layer over the gate and source drain regions wherein the second stress-inducing layer imparts a same type stress as said first stress-inducing layer;
- subjecting the first and second stress-inducing layer to a thermal anneal to cause a stress to form in the channel region, wherein the first stress-inducing layer imparts a compressive stress to the backside of the semiconductor wafer and imparts a tensile stress to the channel region and the second stress-inducing layer imparts a tensile stress to the channel region;
- forming interlevel dielectrics over the transistors;
- and
- forming interconnects in the interlevel dielectrics that interconnect the transistors to form an operative integrated circuit.
Dependencies are inferred from the claim text.