US 7,402,496 B2Granted

Complementary metal-oxide-semiconductor device and fabricating method thereof

AssigneeUnited Microelectronics Corp.

InventorsChe-Hung Liu, Po-Lun Cheng, Chun-An Lin, Li-Yuen Tang, Hung-Lin Shih, Ming-Chi Fan, Hsien-Liang Meng, Jih-Shun Chiang

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Abstract

A complementary metal-oxide-semiconductor (CMOS) device includes a substrate with a first active region and a second active region; a first gate structure and a second gate structure, respectively disposed on the first active region and the second active region; a first spacer structure and a second spacer structure respectively disposed on sidewalls of the first gate structure and the second gate structure; a first LDD and a second LDD respectively disposed in the substrate at both sides of the first gate structure and the second gate structure; an epitaxial material layer, disposed in the first active region and located on a side of the first LDD; and a passivation layer, disposed on the first gate structure, the first spacer structure, and the first LDD and covering the second active region, wherein the passivation layer comprises a carbon-containing oxynitride layer.

Claims23

Dependent claims

A method of fabricating a complementary metal-oxide-semiconductor device, comprising:

providing a substrate having an isolation structure dividing the substrate into a first active region and a second active region, wherein the first active region has a first gate structure, a first spacer structure and a first LDD formed therein and the second active region has a second gate structure, a second spacer structure and a second LDD formed therein;
forming a passivation layer conformally over the substrate, wherein the passivation layer comprises a carbon-containing oxynitride layer;
forming a photoresist layer on the passivation layer of the second active region;
performing an etching process by using the first photoresist layer as a mask to remain a portion of the first passivation layer completely covering the first gate structure and the first spacer structure
removing the photoresist layer;
removing a portion of the exposed substrate in the first active region by using the passivation layer as a mask to form a trench in the substrate;
filling an epitaxial material layer in the trench to serve as a first conductive source/drain (S/D) region;
removing the passivation layer;
and
forming a doped region on the substrate in the second active region to serve as a second conductive S/D region.

7 more elements

A method of fabricating a complementary metal-oxide-semiconductor device, comprising:

providing a substrate having an isolation structure dividing the substrate into a first active region and a second active region, wherein the first active region has a first gate structure, a first spacer structure and a first LDD formed therein and the second active region has a second gate structure, a second spacer structure and a second LDD formed therein;
forming a first passivation layer to conformally cover the substrate, wherein the first passivation layer is a carbon-containing oxynitride layer;
forming a first photoresist layer on the substrate to cover the first passivation layer on the second active region;
performing an etching process by using the photoresist layer as a mask to remain a portion of the first passivation layer completely covering the first gate structure and the first spacer structure,
removing the first photoresist layer;
removing a part of the exposed substrate in the first active region by using the first passivation layer as a mask to form a first trench in the substrate;
filling a first epitaxial material layer in the first trench to serve as a first conductive S/D region;
removing the first passivation layer;
forming a second passivation layer to conformally cover the substrate, wherein the second passivation layer is a carbon-containing oxynitride layer;
forming a second photoresist layer on the substrate to cover the second passivation layer on the first active region;
performing an etching process by using the second photoresist layer as a mask to remain a portion of the second passivation layer completely covering the second gate structure and the second spacer structure
removing the second photoresist layer;
removing a portion of the exposed substrate in the second active region by using the second passivation layer as a mask to form a second trench in the substrate;
and
filling a second epitaxial material layer in the first trench to serve as a second conductive S/D region.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/530,480Filed 11 Sep 2006
Published: US 2008/0061366 A113 Mar 2008
Granted: 22 Jul 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10D 30/792
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: comprising applied insulating layers, e.g. stress liners
H10D 30/601
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
H10D 30/608
Having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs: having non-planar bodies, e.g. having recessed gate electrodes
H10D 62/021
Manufacture or treatment: forming source or drain recesses by etching e.g. recessing by etching and then refilling