Charge-trapping memory device and methods for operating and manufacturing the cell

A method for manufacturing a memory device, the method comprising:

• providing a semiconductor body;
• forming a gate dielectric layer over the semiconductor body;
• forming a gate electrode layer over the gate dielectric layer;
• structuring the gate electrode layer to form a gate electrode with sidewalls;
• performing an etching process to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of said gate electrode;
• after said gate dielectric has been removed, forming boundary layers on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where said gate dielectric has been removed thereby leaving spaces;
• depositing charge-trapping layer material to fill the spaces;
• and
• forming source and drain regions in the semiconductor body adjacent the gate electrode;
• wherein the charge-trapping layer material has a layer thickness that is provided, relative to the layer thickness of the gate dielectric in an area between the filled spaces and a total layer thickness of said gate dielectric in an area of said filled spaces, in such a manner that a positive voltage applied to the gate electrode and provided for inducing tunneling of electrons into the charge-trapping layer generates an electric field strength in said area of the filled spaces that is larger or equal to an electric field strength in said area between the filled spaces during a process of erasure of the memory device;
• and
• wherein the gate dielectric comprises silicon dioxide and the charge-trapping layer comprises silicon nitride, and wherein a ratio of said layer thickness of said charge-trapping layer and said layer thickness of said gate dielectric in said area between said strips is between 0.3 and 0.7.

A method of making a charge-trapping memory cell, the method comprising:

• providing a semiconductor body;
• forming a gate dielectric over a surface of the semiconductor body, the gate dielectric having a layer thickness, wherein a charge-trapping layer is formed within the gate dielectric, the charge-trapping layer comprising two strips that are each located between an upper boundary of a junction and the gate-electrode and which are enclosed by said gate dielectric, the strips being formed of a material with higher relative permittivity than the gate dielectric;
• forming a gate electrode over the gate dielectric;
• forming source and drain regions in said semiconductor body adjacent the gate electrode;
• and
• wherein the strips have a layer thickness that is provided relative to the layer thickness of the gate dielectric in an area between the strips and a total layer thickness of said gate dielectric in an area of said strips in such a manner that a positive voltage applied to the gate electrode and provided for inducing a Fowler-Nordheim-tunnelling of electrons into the charge-trapping layer generates an electric field strength in said area of the strips, which is larger or equal to an electric field strength in said area between the strips during a process of erasure of the memory cell;
• and
• wherein the gate dielectric comprises silicon dioxide and the charge-trapping layer comprises silicon nitride, and wherein a ratio of said layer thickness of said charge-trapping layer and said layer thickness of said gate dielectric in said area between said strips is between 0.3 and 0.7.

A method of making a charge-trapping memory cell, the method comprising:

• providing a semiconductor body;
• forming a gate dielectric over a surface of the semiconductor body, the gate dielectric having a layer thickness, wherein a charge-trapping layer is formed within the gate dielectric, the charge-trapping layer comprising two strips that are each located between an upper boundary of a junction and the gate-electrode and which are enclosed by said gate dielectric, the strips being formed of a material with higher relative permittivity than the gate dielectric;
• forming a gate electrode over the gate dielectric;
• forming source and drain regions in said semiconductor body adjacent the gate electrode;
• and
• wherein the strips have a layer thickness that is provided relative to the layer thickness of the gate dielectric in an area between the strips and a total layer thickness of said gate dielectric in an area of said strips in such a manner that a positive voltage applied to the gate electrode and provided for inducing a Fowler-Nordheim-tunnelling of electrons into the charge-trapping layer generates an electric field strength in said area of the strips, which is larger or equal to an electric field strength in said area between the strips during a process of erasure of the memory cell;
• and
• wherein the gate dielectric comprises silicon dioxide and the charge-trapping layer comprises A1203, and wherein a ratio of said layer thickness of said charge-trapping layer and said layer thickness of said gate dielectric in said area between said strips is between 0.25 and 0.6.

A method of making a charge-trapping memory cell, the method comprising:

• providing a semiconductor body;
• forming a gate dielectric over a surface of the semiconductor body, the gate dielectric having a layer thickness, wherein a charge-trapping layer is formed within the gate dielectric, the charge-trapping layer comprising two strips that are each located between an upper boundary of a junction and the gate-electrode and which are enclosed by said gate dielectric, the strips being formed of a material with higher relative permittivity than the gate dielectric;
• forming a gate electrode over the gate dielectric;
• forming source and drain regions in said semiconductor body adjacent the gate electrode;
• and
• wherein the strips have a layer thickness that is provided relative to the layer thickness of the gate dielectric in an area between the strips and a total layer thickness of said gate dielectric in an area of said strips in such a manner that a positive voltage applied to the gate electrode and provided for inducing a Fowler-Nordheim-tunnelling of electrons into the charge-trapping layer generates an electric field strength in said area of the strips, which is larger or equal to an electric field strength in said area between the strips during a process of erasure of the memory cell;
• and
• wherein the gate dielectric comprises silicon dioxide and the charge-trapping layer comprises HfO2, and wherein a ratio of said layer thickness of said charge-trapping layer and said layer thickness of said gate dielectric in said area between said strips is between 0.2 and 0.5.