Method of fabricating a thin film transistor array substrate

A method of fabricating a thin film transistor array substrate, the method comprising:

• forming a gate pattern including a gate line and a gate electrode on a substrate;
• forming a gate insulating film, an amorphous silicon layer and an n+ amorphous silicon layer on the substrate provided with the gate pattern, and forming a source/drain metal layer containing at least one material of tungsten silicide (WSix), cobalt silicide (CoSix) or nickel silicide (NiSix);
• wherein the gate pattern, the gate insulating film, the amorphous silicon layers, and the source/drain metal layers are all formed by PECVD or MOCVD without removing the substrate from a processing environment in which the chemical vapor deposition process occurs;
• patterning the amorphous silicon layer, the n+ amorphous silicon layer and the source/drain metal layer to provide a semiconductor pattern and a source/drain pattern including the data line, the source electrode and the drain electrode formed on the semiconductor pattern;
• wherein patterning the amorphous silicon layer, the n+ amorphous silicon layer and the source/drain metal layer include patterning the source/drain metal layer by wet etching process, simultaneously patterning the amorphous silicon layer and the n+ amorphous silicon layer by dry etching process, removing a photo resist pattern by ashing process, forming the source electrode and the drain electrode by etching process;
• forming a protective film having a contact hole exposing a portion of the drain electrode on the substrate provided with the source/drain pattern;
• and
• forming a pixel electrode connected, via the contact hole, to the drain electrode.