Optimized transistor for imager device

A method of forming an imager pixel with mitigated dark current leakage, comprising:

• forming a first transistor adjacent a photodiode at a first side of said first transistor, said first transistor having a single active area extension region at a second side of said first transistor opposite said first side;
• and
• forming a floating diffusion region on said second side of said first transistor and in said substrate, wherein said floating diffusion region and said single active area extension region are laterally spaced away from a gate of said first transistor by a portion of said substrate.

A method of forming an imager pixel with mitigated leakage and dark current, comprising:

• forming a first transistor gate adjacent a photodiode at a first side of said first transistor, said first transistor having a gate and a single active area extension region at a second side of said first transistor gate opposite said first side and a threshold voltage adjustment implant below said transistor;
• forming a second transistor having a gate on the second side of said first transistor;
• forming a floating diffusion region between the first and second transistor gates and closer to said second transistor gate.

A method of forming an imager pixel with mitigated leakage and dark current, comprising forming a transfer transistor gate adjacent a photodiode at a first side of said transfer transistor gate, said transfer transistor gate having an associated single active area extension region at a second side of said transfer transistor gate opposite said first side, wherein said transfer transistor gate has an increased gate length relative to any other transistor gate of said imager pixel and said active area extension region is laterally spaced away from said transfer transistor gate.

A method of forming an imager pixel with mitigated leakage and dark current, comprising forming a transistor adjacent a photodiode at a first side of said transistor, said transistor having an active area and a single active area extension region at a second side of said transistor opposite said first side, where said active area and said active area extension region are laterally spaced away from a gate of said transistor by a portion of a substrate supporting said transistor.