Physically highly secure multi-chip assembly

A method for providing a physically secure multi-chip assembly, the method comprising the steps of:

• mounting a first die on a first planar surface of a substrate such that electrical contacts on a first surface of the first die are located between the first surface of the first die and the first planar surface of the substrate;
• mounting a second die on the first planar surface of the substrate such that electrical contacts on a first surface of the second die are located between the first surface of the second die and the first planar surface of the substrate;
• providing a first conductive pathway that is connected to at least one of the electrical contacts of the first die, at least a portion of the first conductive pathway being located within the substrate;
• providing a second conductive pathway that is connected to at least one of the electrical contacts of the second die, at least a portion of the second conductive pathway being located within the substrate;
• providing a plurality of electrical conductors that surround at least part of the first and second conductive pathways;
• and
• detecting a break in continuity of one or more of the electrical conductors.