Method and apparatus for characterizing arrays using cell-based timing elements
AssigneeAdvanced Micro Devices, Inc.
InventorsRussell Schreiber, David M. Newmark, Joe Spector
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Abstract
The present invention provides a method and apparatus for characterizing a memory array. The method includes accessing information indicative of a transistor-level circuit design of a column of a memory array and determining at least one component of a cell representative of the column of the memory array based on the information indicative of the transistor-level circuit design and at least one timing rule for at least one signal associated with the column of the memory array. The method also includes determining at least one time delay associated with the cell based on the at least one component of at least one cell.
Claims28
A method, comprising:
- accessing information indicative of a transistor-level circuit design of a column of a memory array;
- determining at least one component of a cell representative of the column of the memory array based on the information indicative of the transistor-level circuit design and at least one timing rule for at least one signal associated with the column of the memory array;
- and
- determining at least one time delay associated with the cell based on said at least one component of at least one cell.
An apparatus, comprising:
- means for accessing information indicative of a transistor-level circuit design of a column of a memory array;
- means for determining at least one component of a cell representative of the column of the memory array based on the information indicative of the transistor-level circuit design and at least one timing rule for at least one signal associated with the column of the memory array;
- and
- means for determining at least one time delay associated with the cell based on said at least one component of at least one cell.
An apparatus, comprising:
- a processing unit configured to:
- access information indicative of a transistor-level circuit design of a column of a memory array;
- determine at least one component of a cell representative of the column of the memory array based on the information indicative of the transistor-level circuit design and at least one timing rule for at least one signal associated with the column of the memory array;
- and
- determine at least one time delay associated with the cell based on said at least one component of at least one cell.
Dependencies are inferred from the claim text.