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AssigneeInternational Business Machines Corporation
InventorsBodo Hoppe, Christoph Jaeschke, Johannes Koesters
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The present invention relates to a method for verifying the proper operation of a digital logic circuit. In order to add a useful alternative in the field of functional, exhaustive simulation and of symbolic simulation, it is proposed to perform the steps of: a) marking a net with an additional property other than a bit value, wherein both said bit value and said additional property are valid at said net at a given time; b) propagating the marking of the net according to a set of predetermined semantic rules, wherein the set of predetermined semantic rules are defined according to a predetermined simulation aim; and c) generating an output at a predetermined downstream location of the digital logic circuit, said output providing an information, if or if not said property has propagated through the circuit to said predetermined downstream location or not.
A method for performing a verification of a logic circuit, wherein the logic circuit comprises nets and gates and wherein output values are calculated for each gate dependent on a predetermined input bit setting, the method being characterized by the steps of:
Dependencies are inferred from the claim text.