Isolated pwell tank verification using node breakers

A method for implementing a design rule for transferring a circuit design from a schematic form to a layout form to facilitate forming a circuit on a semiconductor substrate, comprising:

• checking a layout for an instance where multiple isolated pwells are coupled to a same node;
• inserting a node breaker in the layout between isolated pwells coupled to the same node;
• checking the layout for an instance where one or more isolated pwells are shorted to the semiconductor substrate;
• and
• inserting a node breaker in the layout between the semiconductor substrate and isolated pwells shorted to the semiconductor substrate.

A method of verifying a circuit design in layout and schematic forms, comprising:

• checking for one or more instances where multiple isolated pwells are coupled to a same node in a layout of a circuit and where an isolated pwell is coupled to a substrate;
• inserting a node breaker in the layout between isolated pwells coupled to the same node and between the substrate and isolated pwells coupled to the substrate;
• and
• inserting node breakers at corresponding locations in a circuit schematic.