Method for fast incremental calculation of an impact of coupled noise on timing

A method of incrementally calculating an impact of coupling noise on timing of an integrated circuit (IC) design comprised of a plurality of logic stages, the method comprising:

• a) performing an initial timing analysis on the integrated circuit design to determine a first impact of the coupling noise on the timing on at least one victim stage of the integrated circuit design;
• b) performing at least one design change on the IC design;
• c) responsive to the at least one design change, calculating a second impact of the coupling noise on the timing of at least one victim stage where the at least one design change was made and downstream thereof;
• d) providing results of the calculated second impact to a timing analysis tool to adjust a delay and slew of the at least one victim stage where the at least one design change was made and downstream thereof;
• and
• e) calculating a new K-factor based on a current victim switching window and slew, and a previously-computed aggressor switching window and slew.

A system for incrementally calculating an impact of coupling noise on timing of an integrated circuit (IC) comprised of a plurality of logic stages, the system comprising:

• a) means for performing an initial timing analysis on the IC by calculating sensitivity of delay and slew respectively as a function of a change in effective coupling capacitance to determine a first impact of the coupling noise on the timing;
• b) means for performing at least one design change on the IC;
• c) responsive to the at least one design change, means for calculating a second impact of the coupling noise on the timing of at least one logic stage where the at least one design change was made and downstream thereof;
• and
• d) means for providing results of the calculated second impact to a timing analysis tool to adjust a delay and slew of the at least one logic stage where the at least one design change was made and downstream thereof.

A program storage device readable by a machine, tangibly, embodying a program of instructions executable by the machine to perform method steps for incrementally calculating an impact of coupling noise on timing of an integrated circuit (IC) comprised of a plurality of logic stages, said method steps comprising:

• a) performing an initial timing analysis on the IC by calculating sensitivity of delay and slew respectively as a function of a change in effective coupling capacitance to determine a first impact of the coupling noise on the timing;
• b) performing at least one design change on the IC;
• c) responsive to the at least one design change, calculating a second impact of the coupling noise on the timing of at least one logic stage where the at least one design change was made and downstream thereof;
• and
• d) providing the results of the calculated second impact to a timing analysis tool to adjust a delay and slew of the at least one logic stage where the at least one design change was made and downstream thereof.