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US 7,398,490 B2Granted
Digital circuit layout techniques using binary decision diagram for identification of input equivalence
OwnerDavid E Wallaceinventor
Life of this patent
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Abstract
A technique for analyzing digital circuits to identify pin swaps is provided for circuit layout and similar tasks in which the circuit is first decomposed into regions. Logic functions of the regions are decomposed into a directed graph of the logic functions. A swap structure is created in accordance with the directed graph to facilitate identification of input equivalences.
Claims20
A computer-implemented method, comprising:
- decomposing a circuit representation into fanout-free regions, each of the fanout-free regions corresponding to at least one logic function and each of the fanout-free regions comprising an output;
- decomposing the at least one logic function of at least one of the fanout-free regions by generating a binary decision diagram for each output of the at least one of the fanout-free regions;
- identifying equivalent pins by matching pins of gates in the circuit representation with points in a ds-prime graph created using the binary decision diagram;
- and
- using the identified pin equivalence information to determine the input equivalence of the at least one of the fanout-free regions.
2 more elements
One or more computer-readable media comprising computer-executable instructions which, when executed by a processor, perform a method comprising:
- decomposing a circuit representation into fanout-free regions, each of the fanout-free regions corresponding to at least one logic function and each of the fanout-free regions comprising an output;
- decomposing the at least one logic function of at least one of the fanout-free regions by generating a binary decision diagram for each output of the at least one of the fanout-free regions;
- identifying equivalent pins by matching pins of gates in the circuit representation with points in a ds-prime graph created using the binary decision diagram;
- and
- using the identified pin equivalence information to determine the input equivalence of the at least one of the fanout-free regions.
2 more elements
Dependencies are inferred from the claim text.