Yield optimization in router for systematic defects

A method of optimizing router settings to increase integrated circuit yield, comprising:

• reviewing yield data in an integrated circuit manufacturing line to identify structure-specific mechanisms that impact said integrated circuit yield;
• establishing one of a plurality of structural identifiers and one of a plurality of weighting factors for each of said structure-specific mechanisms, comprising
• establishing different structural identifiers for wires comprising different widths,
• establishing weighting factors comprising lower values relative to other weighting factors to structure-specific mechanisms comprising single wires spaced a minimum distance from at least one of double wires and triple wires, and
• establishing structural identifiers and weighting factors for incidence of wires above metal lands;
• modifying said router settings based on said structural identifiers and said weighting factors to minimize layout placement of structures that are known to create systematic defects;
• and
• tuning said router settings to minimize random defects, comprising:
• selecting multiple representative chips,
• performing router test cases by routing each of said chips with a different weighting factor,
• generating graphical data for each of said router test cases,
• performing a critical area analysis for each of said router test cases, and
• selecting a router test case for said tuning of said router settings based on results of said critical area analysis.

A method of optimizing router settings to increase integrated circuit yield, comprising:

• reviewing yield data in an integrated circuit manufacturing line to identify structure-specific mechanisms that impact said integrated circuit yield;
• establishing one of a plurality of structural identifiers for each of said structure-specific mechanisms, comprising establishing different structural identifiers for wires comprising different widths;
• establishing one of a plurality of weighting factors for each of said structure-specific mechanisms, comprising
• establishing higher weighting factors for structure-specific mechanisms comprising wires proximate to multiple wires, relative to other weighting factors,
• establishing weighting factors comprising lower values relative to other weighting factors to structure-specific mechanisms comprising single wires spaced a minimum distance from at least one of double wires and triple wires,
• establishing structural identifiers and weighting factors for incidence of wires above metal lands, and
• establishing structural identifiers and weighting factors for incidence of spacing between single wide lines, double wide lines, and triple wide lines;
• modifying said router settings based on said structural identifiers and said weighting factors to minimize layout placement of structures that are known to create systematic defects;
• and
• tuning said router settings to minimize random defects, comprising:
• selecting multiple representative chips,
• performing router test cases by routing each of said chips with a different weighting factor,
• generating graphical data for each of said router test cases,
• performing a critical area analysis for each of said router test cases, and
• selecting a router test case for said tuning of said router settings based on results of said critical area analysis.

A computer program product comprising a computer usable medium having a computer readable program, wherein the computer readable program, when executed on a computer, causes the computer to perform a method comprising:

• reviewing yield data in an integrated circuit manufacturing line to identify structure-specific mechanisms that impact said integrated circuit yield;
• establishing one of a plurality of structural identifiers and one of a plurality of weighting factors for each of said structure-specific mechanisms, comprising establishing weighting factors comprising lower values relative to other weighting factors to structure-specific mechanisms comprising single wires spaced a minimum distance from at least one of double wires and triple wires;
• modifying said router settings based on said structural identifiers and said weighting factors to minimize systematic defects;
• and
• tuning said router settings to minimize random defects, comprising:
• selecting multiple representative chips,
• performing router test cases by routing each of said chips with a different weighting factor,
• generating graphical data for each of said router test cases,
• performing a critical area analysis for each of said router test cases, and
• selecting a router test case for said tuning of said router settings based on results of said critical area analysis.