Intercommunicating apparatus for duplex system capable of detecting failure thereof
AssigneeNEC Corporation
InventorHirofumi Sudo
Life of this patent
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Abstract
A parity generating circuit in a 0 side receives input signals on respective signal lines and produces a parity bit based on the input signals. A parallel/serial converting circuit multiplexes parallel signals (or input signals) and the parity bit into a serial signal with reference to a timing signal. A serial/parallel converting circuit in a 1 side reproduces parallel signals and a parity signal and produces a parity check timing signal. A parity checking circuit checks a parity of the parallel signals by the use of the parity signal. If normal, a state holding circuit holds outputs of the parity checking circuit as a state signal. If abnormal, held content of the state holding circuit is cleared.
Claims19
A method for transmitting a plurality of intercommunicating signals parallel to one another from a first processor unit to a second processor unit of a duplex processor apparatus, said method comprising the steps of:
- changing said intercommunicating signals supplied from said first processor unit into a serial signal having a redundancy data structure;
- reproducing said intercommunicating signals in the form of parallel signals from said serial signal;
- and
- supplying the reproduced intercommunicating signals to said second processor unit, wherein,
- said step of changing said intercommunicating signals into a serial signal having a redundancy data structure is conducted at a transmitting portion of a duplex processor apparatus at a timing of a first timing signal,
- said intercommunicating signals comprises parallel operation mode signals which include an ACTN signal representative of being an active system, a SYCN signal representative of being in a duplex operation, and a RUNN signal representative of a processor being in execution, the operation mode signals defining active and standby systems in a duplex processor apparatus,
- prior to said reproducing step, the further step of sending the serial output signal to a receiving portion of the duplex processor apparatus,
- said reproducing step further produces a parity check timing signal obtained by reproducing the first timing signal, and
- at the receiving portion, the further step of, with said reproduced redundancy data, evaluating said redundancy data for an error in said reproduced intercommunicating signals.
A method for transmitting a plurality of intercommunicating signals parallel to one another from a first processor unit to a second processor unit of a duplex processor apparatus, said method comprising the steps of:
- at a transmitting portion of a duplex processor apparatus, at a timing of a first timing signal, changing a set of plural parallel intercommunicating signals supplied from a first processor unit into a serial output signal having a redundancy data structure, said supplied parallel intercommunicating signals comprising operation mode signals which include an ACTN signal representative of being an active system, a SYCN signal representative of being in a duplex operation, and a RUNN signal representative of a processor being in execution, the operation mode signals defining active and standby systems in a duplex processor apparatus;
- sending the serial output signal to a receiving portion of the duplex processor apparatus;
- at the receiving portion, reproducing, from said serial signal, said intercommunicating signals and said redundancy data in the form of parallel signals;
- with said reproduced redundancy data, evaluating said redundancy data for an error in said reproduced intercommunicating signals;
- and
- supplying the reproduced intercommunicating signals to said second processor unit.
Dependencies are inferred from the claim text.