Loop-back method for measuring the interface timing of semiconductor devices with the aid of signatures and/or parity methods

A semiconductor device, comprising:

• an input driver;
• an output driver;
• and
• circuitry configured to:
• receive test input data;
• perform a test of the semiconductor device using the test input data to obtain test output data, the test comprising:
• outputting the test input data from the output driver;
• and
• inputting the output test input data into the input driver, thereby generating test output data from the test input data, wherein the output driver is signal-connected to a first data pad, and the first data pad is signal-connected to a first external data contact, and the first external data contact is signal-connected to a second external data contact, and the second external data contact is signal-connected to a second data pad, and the second data pad is signal connected to the input driver, during the test to enable the test input data to be simultaneously output from and input to the semiconductor device;
• and
• create a data test result from the test output data.

A semiconductor device, comprising:

• means for inputting;
• means for outputting;
• means for connecting;
• and
• means for controlling configured to:
• receive test input data;
• perform a test using the test input data to generate test output data, the test comprising:
• outputting the test input data from the means for outputting;
• and
• inputting the output test input data into the means for inputting, thereby generating test output data from the output test input data, wherein the means for inputting and the means for outputting are connected during the test to enable the test input data to be simultaneously output from and input to the semiconductor device, and
• the means for connecting the means for inputting and the means for outputting is external to the semiconductor device;
• and
• create a data test result from the test output data.

A method for performing a test of a memory device, the method comprising:

• reading test input data into a memory array of the memory device from an external testing device;
• outputting the test input data in the memory array from an output driver of the memory device;
• inputting the test input data output by the output driver into an input driver of the memory device, thereby generating test output data, wherein the output driver is signal-connected to a first data pad, the first data pad is signal-connected to a first external data contact, the first external data contact is signal-connected to a second external data contact, the second external data contact is signal-connected to a second data pad, and the second data pad is signal connected to the input driver;
• and
• determining if the test was successful by determining if the output test input data was correctly input into the input driver.

A memory device comprising:

• a device for providing test input data;
• an output driver;
• an input driver;
• a first data pad;
• a second data pad;
• test circuitry configured to:
• connect the output driver to the first data pad;
• and
• connect the input driver to the second data pad, wherein the first data pad is signal-connected to a first external data contact, the first external data contact is signal-connected to a second external data contact, and the second external data contact is signal-connected to a second data pad, and wherein the test input data are simultaneously output from the output driver and input to the input driver to obtain test output data;
• and
• a data test result generating device configured to create a data test result from the test output data.