Automatic fault-testing of logic blocks using internal at-speed logic-BIST
AssigneeGenesis Microchip Inc.
InventorsVenkat Chary Mushirabad, Rajanatha Shettigara
Life of this patent
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Abstract
System and method for automatic fault-testing of a logic block and the interfaces of macros with logic gates inside a chip, using an at-speed logic-BIST internal to the chip. Following an initialization of internal storage elements, a set of test signals are generated and processed by the logic block. The output of the logic block is accumulated into a signature and compared to a reference signature to detect faults. Testing can be performed on an ATE (Automatic Test Equipment) using a simple test vector, or can be performed by a field engineer on the actual board comprising the chip.
Claims32
A semiconductor device, comprising:
- a logic block having a set of flip-flops and memories connected to a clock signal and a reset signal;
- a pattern generator for generating a set of test signals for processing by the logic block;
- a signature accumulator for producing a test signature based on a set of outputs produced by the logic block upon processing the test signals;
- and
- a built-in self-test (logic-BIST) circuit for initializing the flip-flops and memories by writing to the flip-flops and memories known values of the reset signal during a same number of clock cycles and initiating testing of the logic block;
- wherein initializing the flip-flops and memories causes them to simultaneously store the known values despite timing variations or propagation delays of the reset signal across the flip-flops and memories.
A method for testing a logic block having a set of flip-flops connected to a clock signal and a reset signal, the method comprising:
- initializing the set of flip-flops by writing to the flip-flops known values of the reset signal during a same number of clock cycles;
- generating a set of test signals for processing by the logic block;
- and
- producing a test signature based on a set of outputs produced by the logic block upon processing the test signals;
- wherein initializing the set of flip-flops causes them to simultaneously store the known values despite timing variations or propagation delays of the reset signal across the set of flip-flops.
A method for testing a semiconductor device having a logic block, a pattern generator, a signature accumulator and a built-in self test (logic-BIST) circuit, comprising:
- causing the logic-BIST circuit to perform the following:
- (a) initializing a set of flip-flops and memories of the logic block, the set of flip-flops connected to a clock signal and a reset signal, by writing to the flip-flops and memories known values of the reset signal during a same number of clock cycles;
- (b) triggering the pattern generator to generate a set of test signals for processing by the logic block;
- and
- (c) causing the signature accumulator to produce a test signature based on a set of outputs produced by the logic block upon processing the test signals;
- and
- comparing the test signature to a reference signature, the reference signature representing the result of fault-free processing of the set of test signals by the logic block;
- wherein initializing the set of flip-flops and memories causes them to simultaneously store the known values despite timing variations or propagation delays of the reset signal across the set of flip-flops.
Computer program product for testing a logic block having a set of flip-flops connected to a clock signal and a reset signal, comprising:
- computer code for initializing the set of flip-flops by writing to the flip-flops known values of the reset signal during a same number of clock cycles;
- computer code for generating a set of test signals for processing by the logic block;
- and
- computer code for producing a test signature based on a set of outputs produced by the logic block upon processing the test signals;
- and
- computer readable medium for storing the computer code;
- wherein initializing the set of flip-flops causes them to simultaneously store the known values despite timing variations or propagation delays of the reset signal across the set of flip-flops.
Dependencies are inferred from the claim text.