Semiconductor device with memory and method for memory test
AssigneeKabushiki Kaisha Toshiba
InventorsKeiichi Kushida, Osamu Hirabayashi
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Abstract
A semiconductor device is disclosed which includes a data memory which stores data and a code memory which stores an ECC code corresponding to the data. The semiconductor device includes an ECC unit which outputs, to the data memory as the data, a test pattern required to test the data memory, and which generates, from the test pattern, code information having an error checking function, and outputs the code information to the code memory as the ECC code.
Claims10
A semiconductor device comprising:
- a data memory which stores data;
- a code memory which stores an ECC code for a test corresponding to the data;
- an ECC circuit which supplies the data memory with a test pattern for detecting a bit error for all cells of the data memory, generates code data as the ECC code from the test pattern using a Hamming matrix which meets predetermined conditions, and supplies the code memory with the code data, the ECC circuit generating the code data for detecting a bit error for all cells of the code memory using a transposed matrix of the test pattern and the Hamming matrix;
- and
- a test circuit which simultaneously tests the data memory and the code memory based on the test pattern written in the data memory and the code data generated by the ECC circuit.
A method of memory test which is applied to a semiconductor device including a data memory which stores data and a code memory which stores an ECC code for a test corresponding to the data, the method comprising the steps of:
- generating a test pattern required to execute a test for detecting a bit error for all cells of the data memory;
- outputting the test pattern to the data memory;
- generating code data as the ECC code for detecting a bit error for all cells of the code memory using a Hamming matrix which meets predetermined conditions and a transposed matrix of the test pattern and the Hamming matrix;
- and
- simultaneously testing the data memory and the code memory based on the test pattern written in the data memory and the code data generated.
Dependencies are inferred from the claim text.