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US 7,398,414 B2Granted
Clocking system including a clock controller that uses buffer feedback to vary a clock frequency
AssigneeGallitzin Allegheny LLC
InventorRobert Warren Sherburne, Jr.
Life of this patent
Estimating the term…
Abstract
A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; one or more clock controllers having clock outputs coupled to the clock inputs of the processing units, the controller operating varying the clock frequency of each processing unit to optimize speed and processing power for a task; and a high-density memory array core coupled to the processing units.
Claims19
An integrated circuit comprising:
- a first processor unit of the integrated circuit capable of receiving a first clock to control the first processor unit;
- a first buffer capable of receiving data from an output of the first processor unit, the first buffer configured to provide a feedback signal to a first clock controller;
- a second processor unit of the integrated circuit capable of receiving the data from the first buffer and configured to receive a second clock to control the second processor unit;
- and
- the first clock controller capable of controlling the first clock based on the feedback signal.
2 more elements
A system comprising:
- an integrated circuit including a digital portion and an analog portion, the digital portion having:
- a reconfigurable processor core including:
- a first processor capable of receiving a first clock to control the first processor;
- a first buffer capable of receiving data from an output of the first processor, the first buffer configured to provide a feedback signal to a first clock controller;
- a second processor capable of receiving the data from the first buffer and configured to receive a second clock to control the second processor;
- and
- the first clock controller capable of controlling the first clock based on the feedback signal;
- and
- the analog portion having radio frequency (RF) circuitry capable of communicating baseband data from the reconfigurable processor core.
6 more elements
A method comprising:
- clocking a first processor of an integrated circuit with a first clock;
- clocking a second processor of the integrated circuit with a second clock, the second clock different than the first clock;
- clocking a buffer coupled to provide data from the first processor to the second processor with the first clock;
- using at least one clock controller to generate a frequency of the first clock and the second clock from a third clock to control the first processor and the second processor;
- and
- varying the first clock based on a feedback signal from the buffer.
3 more elements
Dependencies are inferred from the claim text.