Memory device signaling system and method with independent timing calibration for parallel signal paths

A memory system, comprising:

• a memory component comprising a single integrated circuit;
• and
• a memory controller coupled to the first memory component by a first signal, via a first data path, and by a second signal, via a second data path distinct from the first data path;
• the memory controller including:
• a first circuit to receive a first symbol on the first signal by sampling the first signal using a first timing offset relative to a reference clock signal;
• a second circuit to receive a second symbol on the second signal by sampling the second signal using a second timing offset relative to the reference clock signal, wherein the first timing offset is different from the second timing offset;
• and
• calibration apparatus to combine the first margin timing offset and the second margin timing offset to generate the first timing offset.

A memory controller for use in conjunction with a memory component, comprising:

• an interface to transmit a first signal and a second signal to the memory component, wherein the first signal comprises a first symbol and the second signal comprises a second symbol, the interface to transmit the first signal via a first data path and to transmit the second signal via a second data path distinct from the first data path, the memory component comprising a single integrated circuit;
• a first circuit to transmit the first signal by driving the first symbol using a first timing offset relative to a reference clock signal;
• a second circuit to transmit the second signal by driving the second symbol using a second timing offset relative to the reference clock signal;
• wherein the first timing offset is different from the second timing offset, and
• calibration apparatus to combine the first margin timing offset and the second margin timing offset to generate the first timing offset.

A memory system, comprising:

• a memory component comprising a single integrated circuit;
• and
• a memory controller coupled to the first memory component by a first signal, via a first data path, and by a second signal, via a second data path distinct from the first data path;
• the memory controller including:
• a first circuit to transmit the first signal by driving the first symbol using a first timing offset relative to a reference clock signal;
• a second circuit to transmit the second signal by driving the second symbol using a second timing offset relative to the reference clock signal, wherein the first timing offset is different from the second timing offset, and
• calibration apparatus to combine the first margin timing offset and the second margin timing offset to generate the first timing offset.

A memory controller for use in conjunction with a memory component, comprising:

• an interface to receive, during a memory read operation, a first signal from the memory component, wherein the first signal comprises a first symbol;
• a first circuit to receive the first signal by sampling the first symbol using a first timing offset relative to a reference clock signal, wherein the first timing offset corresponds to an average of a first margin timing offset and a second margin timing offset during the memory read operation;
• and
• calibration apparatus to combine a first margin timing offset and a second margin timing offset to generate the first timing offset.