Measure controlled delay with duty cycle control
AssigneeMicron Technology, Inc.
InventorTyler J. Gomm
Life of this patent
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Abstract
The disclosed embodiments relate to circuits that produce synchronized output signals. More specifically, there is provided a synchronization circuit adapted to receive an input signal, the synchronization circuit comprising a delay monitor adapted to produce a delayed input signal, a counter adapted to determine a difference between the input signal and the delayed input signal and produce a coarse timing signal in response thereto, a circuit adapted to produce a fine timing signal based on the input signal, and a circuit adapted to combine the coarse timing signal and the fine timing signal to produce an output signal.
Claims20
A synchronization circuit configured to receive an input signal, the synchronization circuit comprising:
- a delay monitor configured to produce a delayed input signal;
- a counter configured to determine a difference between the input signal and the delayed input signal and produce a coarse timing signal in response thereto;
- a circuit comprises a ring oscillator and a plurality of latches, configured to produce a fine timing signal based on the input signal;
- and
- a circuit configured to combine the coarse timing signal and the fine timing signal to produce an output signal;
- wherein the synchronization circuit is an open loop circuit.
A method comprising:
- producing a delayed input signal from an input signal;
- determining a difference between the input signal and the delayed input signal using an up/down counter;
- producing a coarse timing signal based on the difference between the input signal and the delayed input signal during a first time interval wherein the up/down counter counts incrementally;
- producing a fine timing signal based on the input signal during a second time interval wherein the up/down counter counts decrementally;
- combining the coarse timing signal and the fine timing signal;
- and
- generating an output based on the combination of the coarse timing signal and the fine timing signal.
A synchronization circuit comprising:
- means for producing a delayed input signal from an input signal;
- means for determining a difference between the input signal and the delayed input signal;
- means for producing a coarse timing signal based on the difference between the input signal and the delayed input signal;
- means for producing a fine timing signal based on the input signal;
- and
- means for combining the coarse timing signal and the fine timing signal;
- wherein the synchronization circuit is an open loop circuit.
Dependencies are inferred from the claim text.