Utilizing paging to support dynamic code updates
AssigneeIntel Corporation
InventorJohn C. Rudelic
Life of this patent
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AssigneeIntel Corporation
InventorJohn C. Rudelic
Estimating the term…
A code object and flash memory may be updated by storing a new code object in the flash memory. Then, a pointer from a page table may be redirected to point to the new code object. The old code object may then be deleted. As a result, code can be updated without the need for rebooting by using the memory management unit and its page table capability.
A method comprising:
An article comprising a medium storing instructions that, if executed, enable a processor-based system to:
A system comprising:
Dependencies are inferred from the claim text.
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Immediately runnable code: execute-in-place [XIP]
Software deployment: updates
Computing and data processing
Term ended 24 Feb 2026 (estimated)
This invention relates generally enabling updates of code objects stored on a flash memory.
Typical code update mechanisms require rebooting of the processor-based system for the update to be installed. To update code objects in an execute-in-place (XiP) system, the system must be rebooted for the update to be applied.
In many cases, it is desirable to manage code, data, and files in flash memory within an open architecture. An execute-in-place system enables this advantage. However, in order to update the code in the flash memory, a reboot is generally required.
FIG. 1 is a system depiction in accordance with one embodiment of the present invention;
FIG. 2 is a software depiction in accordance with one embodiment of the system shown in FIG. 1;
FIG. 3 is a schematic depiction of a random access memory and flash file system in accordance with one embodiment of the present invention;
Referring to FIG. 1, a processor-based system 500 may be a mobile processor-based system in one embodiment. For example, the system 500 may be a handset or cellular telephone. In one embodiment, the system 500 includes a processor 510 with an integral memory management unit (MMU) 530. In other embodiments, the memory management unit 530 may be a separate chip.
The processor 510 may be coupled by a bus 512 to a random access memory (RAM) 514 and a flash memory 518. An input/output (i/o) device 516 may also be coupled to the bus 512. Examples of input/output devices include keyboards, mice, displays, serial buses, parallel buses, and the like.
A wireless interface 520 may also be coupled to the bus 512. The wireless interface 520 may enable any radio frequency protocol, in one embodiment of the present invention, including a cellular telephone protocol. The wireless interface 520 may, for example, include a cellular transceiver and an antenna, such as a dipole, or other antenna.