Dynamic hardware partitioning of symmetric multiprocessing systems

A method including the steps of:

• directing a plurality of compute elements to isolate themselves from each other by disabling included coherent memory link endpoints;
• then
• directing a first plurality of the compute elements to aggregate themselves into a first physical partition by enabling the coherent memory link endpoints included in the first plurality of compute elements;
• then
• directing the first physical partition to isolate itself by disabling the coherent memory link endpoints included in the first plurality of compute elements that are coupled to a disabled one of the coherent memory link endpoints;
• then
• directing a second plurality of the compute elements to aggregate themselves into a second physical partition by enabling the coherent memory link endpoints included in the second plurality of compute elements;
• then
• directing the second physical partition to isolate itself by disabling the coherent memory link endpoints included in the second plurality of compute elements that are coupled to a disabled one of the coherent memory link endpoints;
• and
• wherein each of the coherent memory link endpoints are arranged in pairs that are operable, when the two endpoints of the pair are enabled, to communicate bidirectional shared memory coherency traffic between the pair of compute elements that include the respective memory link endpoint pair;
• wherein the first plurality of compute elements are distinct from the second plurality of compute elements;
• wherein the compute elements are included in a plurality of physically partitionable symmetric multiprocessor modules;
• and
• wherein the compute elements are symmetric multiprocessors.

A method including the steps of:

• (A) in a first processing element, disabling a first plurality of included ports;
• (B) in a second processing element, disabling a second plurality of included ports;
• (C) in the first processing element, enabling the first plurality of ports while the second plurality of ports is disabled;
• (D) in the first processing element, fetching a first instruction at least in part via one of the first plurality of ports;
• (E) in the first processing element, disabling the first plurality of ports after (D);
• (F) in the first processing element, enabling the first plurality of ports after (E);
• (G) in the second processing element, enabling the second plurality of ports after (E);
• (H) in the second processing element, fetching a second instruction at least in part via one of the second plurality of ports and at least in part via one of the first plurality of ports;
• and
• wherein the ports are adapted to send and receive shared memory coherency transactions between the processing elements;
• and
• wherein the second instruction is provided by memory coupled to the first processing element at least in part via one of the shared memory coherency transactions.