US 7,398,374 B2Granted

Multi-cluster processor for processing instructions of one or more instruction threads

AssigneeHewlett-Packard Development Company, L.P.

InventorEric DeLano

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Abstract

The invention provides a processor that processes bundles of instructions preferentially through clusters or execution units according to thread characteristics. The cluster architectures of the invention preferably include capability to process “multi-threaded” instructions. Selectively, the architecture either (a) processes singly-threaded instructions through a single cluster to avoid bypassing and to increase throughput, or (b) processes singly-threaded instructions through multiple processes to increase “per thread” performance. The architecture may be “configurable” to operate in one of two modes: in a “wide” mode of operation, the processor's internal clusters collectively process bundled instructions of one thread of a program at the same time; in a “throughput” mode of operation, those clusters independently process instruction bundles of separate program threads. Clusters are often implemented on a common die, with a core and register file per cluster.

Claims11

Dependent claims

A method for processing bundled instructions through execution units of a processor, comprising the steps of:

determining a mode of operation, wherein the mode of operation comprises one of a throughput mode and a wide mode;
in the throughput mode:
fetching a first bundle of instructions from a first thread of a multiply-threaded program;
distributing the first bundle to a first cluster of the execution units for execution therethrough;
fetching a second bundle of instructions from a second thread of the program;
distributing the second bundle to the first cluster of the execution units for execution therethrough;
fetching a third bundle of instructions from a third thread of the program;
distributing the third bundle to a second cluster of the execution units for execution therethrough;
fetching a fourth bundle of instructions from a fourth thread of the program;
and
distributing the fourth bundle to the second cluster of the execution units for execution therethrough;
wherein the first thread, the second thread, the third thread, and the fourth thread are executing simultaneously:
and
in the wide mode:
fetching a fifth bundle of instructions from a fifth thread of the program;
distributing the fifth bundle to only the first cluster for execution therethrough;
fetching a sixth bundle of instructions from the fifth thread of the program;
and
distributing the sixth bundle to only the second cluster for execution therethrough.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/083,872Filed 27 Feb 2002
Published: US 2003/0163669 A128 Aug 2003
Granted: 8 Jul 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 9/3891
Controlled by multiple instructions, e.g. MIMD, decoupled access or execute: organised in groups of units sharing resources, e.g. clusters
G06F 9/3828
Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage: with global bypass, e.g. between…
G06F 9/3851
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: from multiple instruction streams, e.g. multistreaming
G06F 9/3885
Concurrent instruction execution, e.g. pipeline or look ahead: using a plurality of independent parallel functional units