System and method for processing complex computer instructions
AssigneeSony Corporation Entertainment Inc.
InventorHidetaka Magoshi
Life of this patent
Estimating the term…
Abstract
A system and method for handling complex instructions are provided. The process includes generating a jump instruction from an address which may be embedded in a computer instruction and selecting the original instruction if it was not complex or the jump instruction if it was.
Claims29
A system for processing a computer instruction from a source of such instructions comprising:
- a complex instruction detector having an input and an output, the input accepting computer instructions from the source and the output being indicative of whether the instruction is a member of a set of instructions,
- an address generator having an input and an output, the input accepting computer instructions from the source and the output comprising an address based on the instruction,
- a jump instruction generator having an input and an output, the input being in communication with the address generator output and the output comprising an instruction to jump to the address from the address generator,
- an instruction selector having inputs and an output, the inputs being in communication with the jump instruction generator, the source and the complex instruction detector, the output comprising either the instruction from the source or the instruction from the jump instruction generator depending upon the output of the complex instruction detector.
A method of processing a computer instruction, comprising:
- generating an address associated with the computer instruction;
- generating a jump instruction based on the address;
- determining whether the computer instruction is complex;
- providing both the computer instruction and the jump instruction;
- and
- selecting the jump instruction or the computer instruction based on the result of the step of determining;
- wherein determining whether the computer instruction is complex is performed in parallel with the steps of generating the address and generating the jump instruction.
A system for processing computer instructions between a memory and a processor comprising:
- a complex instruction detector connected to the memory so as to receive computer instructions from the memory and output a value indicative of whether the instruction is a member of a set of instructions;
- an address generator connected to the memory so as to receive computer instructions from the memory and to generate an address;
- a jump instruction generator connected to the address generator;
- and
- an instruction selector connected to the jump instruction generator, the memory, the complex instruction detector and the processor so as to receive:
- jump instructions from the jump instruction generator, computer instructions from the memory, and the value from the complex instruction detector;
- whereby depending on the value from the complex instruction detector, either the jump instruction or the computer instruction is provided by the instruction selector to the processor.
A method of executing a program with a processor, the processor being capable of executing a set of instructions, the method comprising:
- providing an original instruction from a sequence of instructions comprising a program stored in a memory;
- generating an address from the original instruction;
- generating a jump and link instruction to the address, the jump and link instruction comprising an instruction for the processor to execute instructions at the address and then return to the instruction following the original instruction in the program;
- determining whether the original instruction is a complex instruction on an instruction by instruction basis;
- and
- selecting between the jump and link instruction and the original instruction based on the result of the determining.
A system for processing computer instructions between a memory and a processor, the system comprising:
- a complex instruction detector operatively connected to the memory so as to receive computer instructions from the memory, the complex instruction detection being operable to output a value indicative of whether the instruction is a complex instruction on an instruction by instruction basis;
- an address generator operatively connected to the memory so as to receive computer instructions, the address generator being operable to generate an address;
- a jump instruction generator operatively connected to address generator;
- and
- an instruction selector operatively connected to the jump instruction generator, the memory, the complex instruction detector, and the processor so as to receive jump instructions from the jump instruction generator, computer instructions from the memory, and the value from the complex instruction detector;
- whereby depending on the value from the complex instruction detector, either the jump instruction or the computer instruction is selected by the instruction selector and is provided by the instruction selector to the processor.
Dependencies are inferred from the claim text.