Fusing load and alu operations
AssigneeIntel Corporation
InventorsNicholas G. Samra, Stephan J. Jourdan, David J. Sager, Glenn J. Hinton
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Abstract
Fusing a load micro-operation (uop) together with an arithmetic uop. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in a cache memory, un-fused, executed in parallel, and retired in order to optimized cost and performance.
Claims34
A method comprising:
- fetching an instruction from a main memory source;
- decoding said instruction into at least two micro-operations (uops), said at least two uops corresponding to a load operation and an arithmetic operation, respectively;
- fusing said at least two uops into one fused uop;
- storing said fused uop within one cache entry within a cache memory;
- introducing said fused uop to a microprocessor.
An apparatus comprising:
- a rename unit comprising logic to decode a fused micro-operation (uop) into a load child uop and an arithmetic child uop;
- at least two parallel scheduling units coupled to said rename unit;
- at least two parallel execution units coupled to said at least two parallel scheduling units;
- a retirement unit coupled to said at least two parallel execution units logic to reassign fused uop register fields including logic to assign two fused uor source fields to a first and second load child uop source registers.
A system comprising:
- a microprocessor to execute an instruction, said instruction comprising a load micro-operation (uop) and an arithmetic uop, said microprocessor to encode said load uop and arithmetic uop into a fused uop;
- and
- a cache memory coupled to said encoding unit to store said fused uop in one entry of said cache memory logic coupled to the microprocessor to assign two fused uop source fields to a first and second load child uop source registers.
A machine-readable medium having stored thereon a set of instructions, which when executed by a machine, cause said machine to perform a method comprising:
- decoding an instruction into at least two micro-operations (uops);
- fusing said at least two uops into one fused uop;
- storing said fused uop within one cache entry within a cache memory;
- introducing said fused uop to a microprocessor;
- decoding said fused uops into a load child uop and an arithmetic child uop, said decoding comprising assigning two fused uop source fields to a first and second load child uop source registers and assigning a fused uop destination field to a first arithmetic child uop source register and an arithmetic child uop destination register and forwarding a load child uop destination field to a second arithmetic child uop source register.
An apparatus comprising:
- a means for renaming comprising a means for decoding a fused micro-operation (uop) into a load child uop and an arithmetic child uop;
- a means for scheduling said load child uop and said arithmetic child uop in parallel coupled to said means for renaming;
- a means for executing said load child uop and said arithmetic child uop in parallel coupled to said means for scheduling;
- a means for retiring coupled to said means for executing a means for assigning two fused uor source fields to a first and second load child uor source registers.
Dependencies are inferred from the claim text.