Atomic operation involving processors with different memory transfer operation sizes

A cell processor, comprising:

• a data bus
• a main memory coupled to the data bus, the main memory containing one or more task definitions;
• a power processor element (PPE) coupled to the data bus;
• one or more synergistic processing elements (SPE) coupled to the data bus, wherein each SPE has a synergistic processor unit (SPU) and a local store;
• and
• a main memory having embodied at an address therein a primitive, the primitive being of a memory size that is larger than a maximum size for a memory transfer operation with the PPE and less than or equal to a maximum size for a memory transfer operation with the SPE, the primitive including a parity byte and two or more portions, wherein the parity byte includes at least one bit, wherein a value of the parity byte determines which of the two or more portions is a valid portion and which of the two or more portions is an invalid portion.

In processor system having two or more processors including a main memory, a power processor element (PPE) and a synergistic processor element (SPE) that operate on different sized register lines, a method for using the PPE to atomically update a primitive that can be read or written to in a single operation with the SPE, the method comprising the steps of:

• dividing a main memory address containing the primitive into a parity byte and two or more portions, wherein the parity byte includes at least one bit, wherein a value of the parity byte determines which of the two or more portions is a valid portion and which of the two or more portions is an invalid portion, wherein the primitive is of a memory size that is larger than a maximum size for a memory transfer operation with the PPE and less than or equal to a maximum size for a memory transfer operation with the SPE;
• with the PPE, performing a read with reservation of the parity byte,
• with the PPE, writing to one or more subsections of the invalid portion, wherein each subsection is of a size that the PPE can transfer in a single operation,
• with the PPE, performing a conditional write of a new value to the parity byte, and, upon successful completion of the conditional write operation, changing a value of the parity byte with the PPE.

In processor system having two or more processors including a main memory, a power processor element (PPE) and a synergistic processor element (SPE) that have different sized memory transfer capabilities, a method for using the PPE to atomically read a primitive that can be read or written to in a single operation with the SPE, the method comprising the steps of:

• dividing a main memory address containing the primitive into a parity byte and two or more portions, wherein the parity byte includes at least one bit, wherein a value of the parity byte determines which of the two or more portions is a valid portion and which of the two or more portions is an invalid portion, wherein the primitive is of a memory size that is larger than a maximum size for a memory transfer operation with the PPE and less than or equal to a maximum size for a memory transfer operation with the SPE;
• performing a read with reservation of an initial value of the parity byte with the PPE;
• performing successive read operations on one or more subsections of the invalid portion with the PPE, wherein each subsection being of a size that the PPE can transfer in a single operation;
• and
• performing a conditional write upon the parity byte with the initial value with the PPE.