Methods and apparatus for dynamic instruction controlled reconfigurable register file
AssigneeAltera Corporation
InventorsGerald George Pechanek, Edward A. Wolff
Life of this patent
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Abstract
A scalable reconfigurable register file (SRRF) containing multiple register files, read and write multiplexer complexes, and a control unit operating in response to instructions is described. Multiple address configurations of the register files are supported by each instruction and different configurations are operable simultaneously during a single instruction execution. For example, with separate files of the size 32×32 supported configurations of 128×32 bit s, 64×64 bit s and 32×128 bit s can be in operation each cycle. Single width, double width, quad width operands are optimally supported without increasing the register file size and without increasing the number of register file read or write ports.
Claims34
A reconfigurable register apparatus comprising:
- a plurality of register files having a first subset of the plurality of resister files and a second subset of the plurality of register files, each register file is operable to hold a plurality of addressable entries and each addressable entry having a plurality of bits, each register file having write and read ports for accessing an addressable entry;
- a write multiplexer complex connecting to the write ports of each of the register files;
- a read multiplexer complex connecting to the read ports of each of the register files, the read multiplexer complex separate from the write multiplexer complex;
- and
- a decode and control unit connected to the write multiplexer complex and the read multiplexer complex, in response to the decode and control unit receiving a first instruction formatted to identify a first entry in the first subset, the decode and control unit configures the addressability of the plurality of register files to access the first entry, in response to the decode and control unit receiving a second instruction formatted to identify a second entry in the second subset, the decode and control unit configures the addressability of the plurality of register files to access the second entry which spans across the first subset and the second subset.
A reconfigurable storage unit apparatus comprising:
- a plurality of register files, each register file is operable to hold a plurality of entries and each entry having a plurality of bits, each register file having write and read ports;
- a write multiplexer complex connecting to the write ports of each of the register files;
- a read multiplexer complex connecting to the read ports of each of the register files;
- and
- a decode and control unit connected to the write multiplexer complex and the read multiplexer complex, in response to the decode and control unit receiving a first instruction, the decode and control unit configures the addressability of the plurality of register files to operate as a single register file having a K entry by P bit configuration and to access a P bit entry in the plurality of register files, in response to the decode and control unit receiving a second instruction, the decode and control unit configures the addressability of the plurality of register files to operate as a single register file having an L entry by M bit configuration, L≠K and M≠P and to access an M bit entry in the plurality of register files.
A method of reading different size data types from a plurality of register files, the plurality of register files having a first subset of the plurality of register files and a second subset of the plurality of register files, the method comprising:
- receiving a first instruction and a second instruction;
- configuring in response to the first instruction the addressability of the plurality of register files to access a first entry addressed by the first instruction, having a first data type size, and stored in the first subset;
- reading the first entry;
- configuring in response to the second instruction the addressability of the plurality of register files to access a second entry addressed by the second instruction, having a second data type size, and stored across both the first and second subsets;
- and
- reading the second entry.
A method of writing different size data types to a plurality of register files, the plurality of register files having a first subset of the plurality of register files and a second subset of the plurality of register files, the method comprising:
- receiving a first instruction and a second instruction;
- configuring in response to the first instruction the addressability of the plurality of register files to store a first entry addressed by the first instruction and having a first data type size in the first subset;
- writing the first entry to the first subset;
- configuring in response to the second instruction the addressability of the plurality of register files to store a second entry addressed by the second instruction and having a second data type size across both the first subset and the second subset;
- and
- writing the second entry to span across the first subset and the second portion subset.
An apparatus comprising:
- a processor configured to run a first thread of execution and a second thread of execution;
- a plurality of register files having a first subset of the plurality of resister files and a second subset of the plurality of register files, each register file is operable to hold a plurality of entries and each entry having a plurality of bits, each register file having write and read ports;
- and
- a decode and control unit receiving a first instruction from the first thread of execution and a second instruction from the second thread of execution, the first instruction formatted to identify a first entry in the first subset, the second instruction formatted to identify a second entry in the second subset, in response to the decode and control unit receiving the first instruction, the decode and control unit configures the addressability of the plurality of register files to access the first entry, in response to the decode and control unit receiving the second instruction, the decode and control unit configures the addressability of the plurality of register files to access the second entry which spans across the first subset and the second subset.
Dependencies are inferred from the claim text.