Bus system for use with information processing apparatus

An information processing system comprising:

• a first set of lines to be operatively connected to a processor which is operatively connected to cache;
• a second set of lines to be operatively connected to a main memory;
• a third set of lines to be operatively connected to a device, and
• a data transfer unit operatively connected to said first set of lines, said second set of lines, and said third set of lines, for enabling a transfer of data between any arbitrary two of said processor, said memory and said device via corresponding two of said first set of lines, said second set of lines and said third set of lines, independent of another transfer of data between another arbitrary two of said processor, said main memory and said device.