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US 7,398,341 B1Granted
Method and system for programmable input/output transceiver wherein transceiver is configurable to support a plurality of interface standards
AssigneeXilinx, Inc.
InventorJustin L. Gaither
Life of this patent
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Abstract
A method and system for a programmable input/output transceiver is disclosed. A circuit in accordance with the invention includes a programmable transceiver. The programmable transceiver is configured and/or controlled to support an interface standard. A system according to the present invention includes a programmable transceiver and a field-programmable gate array (FPGA) core coupled to program the programmable transceiver.
Claims25
A system comprising:
- a programmable transceiver of a field programmable gate array (FPGA);
- and
- FPGA fabric of the FPGA coupled to program said programmable transceiver, wherein
- said FPGA fabric of the FPGA is configured to program said programmable transceiver to support an interface standard,
- said programmable transceiver is configurable to support at least one of a plurality of interface standards, and
- said programmable transceiver comprises
- a programmable transmitter coupled to said FPGA fabric, and
- said programmable transmitter comprises
- a parallel-to-serial converter,
- a digital-to-analog converter (DAC), and
- a clock multiplier unit (CMU), coupled to said parallel-to-serial converter and said DAC.
8 more elements
An apparatus, comprising:
- a programmable transceiver means for supporting a plurality of interface standards;
- and
- field-programmable gate array (FPGA) fabric means for programming said programmable transceiver means, wherein
- said FPGA fabric means is configured to program said programmable transceiver means,
- said programmable transceiver means comprises a programmable transmitter means for transmitting, coupled to said FPGA fabric, and
- said programmable transmitter means comprises:
- a parallel-to-serial converter means for performing a parallel-to-serial conversion;
- a digital-to-analog converter (DAC) means for performing a digital-to-analog conversion;
- and
- a clock multiplier unit (CMU) means for multiplying a clock, coupled to said parallel-to-serial converter and said DAC.
7 more elements
A system, comprising:
- a programmable transceiver;
- and
- field-programmable gate array (FPGA) fabric coupled to program said programmable transceiver, wherein
- said FPGA fabric is configured to program said programmable transceiver to support an interface standard,
- said programmable transceiver is configurable to support at least one of a plurality of interface standards, and
- said programmable transceiver comprises a programmable transmitter coupled to said FPGA fabric, and wherein
- said programmable transmitter comprises:
- a parallel-to-serial converter;
- a digital-to-analog converter (DAC);
- and
- a clock multiplier unit (CMU), coupled to said parallel-to-serial converter and said DAC.
8 more elements
A system comprising:
- a programmable receiver;
- and
- field-programmable gate array (FPGA) fabric coupled to program said programmable receiver, wherein
- said FPGA fabric is configured to program said programmable receiver, and wherein
- said programmable receiver comprises
- an analog-to-digital converter (ADC),
- a serial-to-parallel converter, and
- a clock/data recovery unit (CDRU), coupled to said ADC and said serial-to-parallel converter.
5 more elements
Dependencies are inferred from the claim text.