Circuit for and method of realigning data
AssigneeXilinx, Inc.
InventorsDouglas E. Thorpe, Farrell L. Ostler
Life of this patent
Estimating the term…
Abstract
A circuit enabling the realignment of data is described. The circuit generally comprises an input multiplexer receiving a first plurality of input data bytes and a second plurality of input data bytes; a switching controller coupled to the input multiplexer and controlling the output of the data bytes from the input multiplexer; a delay register coupled to the input multiplexer and receiving predetermined bytes of the first plurality of input data bytes; and an output multiplexer coupled to the input multiplexer and the delay register. The output multiplexer receives the predetermined bytes of the first plurality of input data bytes and predetermined bytes of the second plurality of input data bytes.
Claims12
A method of realigning data, said method comprising the steps of:
- determining a data alignment of input data comprising a plurality of input bytes coupled to a predetermined number of byte lanes;
- generating an input alignment signal indicating a shift required to realign said plurality of input bytes;
- coupling input bytes of said plurality of input bytes to a delay multiplexer and a pass multiplexer;
- configuring said delay multiplexer and said pass multiplexer according to a shifting configuration based upon said input alignment signal to selectively transfer input data;
- realigning said input bytes of said plurality of input bytes using said delay multiplexer and said pass multiplexer based upon said shifting configuration;
- and
- outputting said realigned data comprising a predetermined number of bytes corresponding to said predetermined number of byte lanes.
A method of realigning data, said method comprising the steps of:
- determining a data alignment of input data comprising a plurality of input bytes coupled to a predetermined number of byte lanes;
- coupling input bytes of a plurality of input bytes to a delay multiplexer and a pass multiplexer;
- configuring said delay multiplexer and said pass multiplexer according to a shifting configuration to selectively transfer said input data to align said input data;
- realigning said input bytes of said plurality of input bytes using said delay multiplexer and said pass multiplexer based upon said shifting configuration;
- generating an output word comprising a predetermined number of bytes corresponding to the predetermined number of byte lanes;
- concatenating a plurality of output words having said predetermined number of bytes;
- and
- outputting said realigned data.
Dependencies are inferred from the claim text.