Integrated circuit input/output interface with empirically determined delay matching

An integrated circuit, comprising:

• an interface to couple to one or more integrated circuits via a plurality of signal traces, wherein at least two signal traces have unmatched signal trace lengths;
• and
• circuitry configured to generate a plurality of trace-specific clock signals having trace-specific phase offsets for the interface using pre-determined empirical information of the signal traces, wherein the trace-specific clock signals compensate for delay differences that are at least partially caused by the unmatched signal trace lengths;
• a circuit to generate a plurality of sub-clock signals based on a reference clock signal;
• and
• a phase interpolator to blend selected ones of the plurality of sub-clock signals and the reference clock signal to generate at least one of the plurality of trace-specific clock signals.

A system, comprising:

• a plurality of signal traces to couple to an integrated circuit, wherein at least two signal traces have unmatched signal trace lengths;
• and
• a memory to couple to the integrated circuit and having stored therein pre-determined empirical information of the signal traces for use by the integrated circuit to generate trace-specific clock signals having trace-specific phase offsets using the pre-determined empirical information, wherein the trace-specific clock signals compensate for delay differences that are at least partially caused by the unmatched signal trace lengths, wherein the pre-determined empirical information comprises at least one of:
• length information of the signal traces, signal flight time information calculated from the lengths of the signal traces, and signal flight time information extracted from a computer-aided design data store.

A system, comprising:

• a plurality of signal traces to couple to an integrated circuit, wherein at least two signal traces have unmatched signal trace lengths;
• a memory to couple to the integrated circuit and having stored therein pre-determined empirical information of the signal traces for use by the integrated circuit to generate trace-specific clock signals having trace-specific phase offsets using the pre-determined empirical information, wherein the trace-specific clock signals compensate for delay differences that are at least partially caused by the unmatched signal trace lengths;
• and
• a circuit to generate a plurality of sub-clock signals from a reference clock signal, and a phase interpolator to blend selected ones of the plurality of sub-clock signals and the reference clock signal to generate at least one of the plurality of trace-specific clock signals.

A system, comprising:

• trace means for coupling a plurality of signals to an integrated circuit, wherein at least two signal traces have unmatched signal trace lengths;
• and
• memory means, coupled to the integrated circuit and having stored therein pre-determined empirical information of the trace means for use by the integrated circuit to generate trace-specific clock signals having trace-specific phase offsets using the pre-determined empirical information, wherein the trace-specific clock signals compensate for delay differences that are at least partially caused by the unmatched signal trace lengths, wherein the pre-determined empirical information comprises at least one of:
• length information of the signal traces, signal flight time information calculated from the lengths of the signal traces, and signal flight time information extracted from a computer-aided design data store.

A system, comprising:

• a package;
• multiple integrated circuits within said package;
• a plurality of signal traces coupling said integrated circuits, wherein at least two signal traces have unmatched signal trace lengths;
• and
• a memory coupled to at least one of the integrated circuits and having stored therein pre-determined empirical information of the signal traces for use by the at least one integrated circuit to generate trace-specific clock signals having trace-specific phase offsets using the pre-determined empirical information, wherein the trace-specific clock signals compensate for delay differences that are at least partially caused by the unmatched signal trace lengths, wherein the pre-determined empirical information comprises at least one of:
• length information of the signal traces, signal flight time information calculated from the lengths of the signal traces, and signal flight time information extracted from a computer-aided design data store.

An integrated circuit comprising:

• multiple circuits on a single integrated circuit;
• a plurality of signal traces coupling said circuits, wherein at least two signal traces have unmatched signal trace lengths;
• and
• a memory coupled to at least one of the circuits and having stored therein pre-determined empirical information of the signal traces for use by the at least one circuit to generate trace-specific clock signals having trace-specific phase offsets using the pre-determined empirical information, wherein the trace-specific clock signals compensate for delay differences that are at least partially caused by the unmatched signal trace lengths, wherein the pre-determined empirical information comprises at least one of:
• length information of the signal traces, signal flight time information calculated from the lengths of the signal traces, and signal flight time information extracted from a computer-aided design data store.