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AssigneeSMI STMicroelectronics S.r.l
InventorsGiuseppe Visalli, Francesco Pappalardo
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In a method for multiplication of floating-point real numbers, encoded in a binary way in sign, exponent and mantissa, the multiplication of the mantissa envisages a step of calculation of partial products, which are constituted by a set of addenda corresponding to the mantissa. In order to reduce the size and power consumption of the circuits designed for calculation, there is adopted a method of binary encoding which envisages setting the first bit of the mantissa to a value 1, in order to obtain a mantissa having a value comprised between 0.5 and 1. Also proposed are methods for rounding of the product and circuits for the implementation of the multiplication method. Also illustrated are circuits for conversion from and to encoding of floating-point teal numbers according to the IEEE754 standard. Preferential application is in portable and/or wireless electronic devices, such as mobile telephones and PDAs, with low power-consumption requirements.
A multiplier device for generating, starting from a first binary digital signal and a second binary digital signal representing respective floating-point real numbers encoded in sign, exponent, and mantissa, an output signal representing a product of said real numbers, the device comprising:
A computer-readable medium which can be directly loaded into the memory of a digital processor and comprises portions of software code that, when the product is run on a computer, implements a method for generating, starting from a first binary digital signal and a second binary digital signal representing respective floating-point real numbers encoded in sign, exponent, and mantissa, an output signal representing a product of said real numbers, the product having a most significant part, the method comprising:
Dependencies are inferred from the claim text.