Loop filter with gear shift for improved fractional-N PLL settling time

A method within a phase-locked loop (PLL), comprising:

• producing an error signal based upon a phase difference between a reference signal and a feedback signal;
• producing an error current based upon the error signal;
• producing a control voltage based upon the error current;
• producing an oscillation based upon the control voltage;
• selecting between a plurality of resistance values in a multi-mode loop filter based upon a two-state multi-mode control signal to provide the selected resistance values;
• selecting between a plurality of capacitance values based upon the two-state multi-mode control signal and operatively coupling selected capacitors to selected resistors to provide the selected capacitance values;
• charging non-selected capacitors while not operationally coupled to the multi-mode loop filter;
• and
• wherein selecting comprises selecting a first set of resistance values and capacitance values in a startup mode and selecting a second set of resistance values and capacitance values in a steady state mode of operation and operating in a startup mode characterized by a wide-band response with a fast settle time and then operating in a steady state mode characterized by narrow-band response with improved filtering.

A loop filter, comprising:

• resistance circuitry coupled to receive an error current;
• capacitance circuitry operatively coupled to the resistance circuitry wherein the capacitance and resistance for a multi-mode loop filter having a specified bandwidth;
• buffer circuitry for charging non-selected capacitors while not operationally coupled to the multi-mode loop filter;
• and
• wherein the capacitance circuitry includes at least one capacitor selectively coupled to the buffer circuitry wherein the at least one capacitor is operatively coupled to reduce the specified bandwidth of the loop filter and to provide filtering in a steady state mode of operation of the loop filter and wherein the at least one capacitor is operatively decoupled from the loop filter in a startup mode of operation while receiving a charge from the buffer circuitry.