Highly parallel switching systems utilizing error correction

An interconnect structure comprising:

• a data switch comprising input ports and output ports;
• and
• a logic that formats a data segment comprising a header H and a payload P into a collection C of sub-segments with a sub-segment s in collection C having a header and a payload, the header including information about a target output port and the payload that is a function of header H and payload P;
• and
• the logic sending the segments in collection C through a plurality of input ports of the interconnect structure to target output ports;
• and
• a logic that reconstructs payload P from the data received at the target output ports of collection C;
• and
• the logic reconstructing payload P in case of error in a payload of a received segment;
• and
• the logic reconstructing payload P in case one of the segments of collection C is misrouted.

An interconnect structure comprising:

• a logic for error detection and/or error correction further comprising:
• a logic that formats a data stream into a plurality of fixed-size segments, the individual segments including a header containing at least a set presence bit and a target address, a payload containing at least segment data and a copy of the target address, and a parity bit designating parity of the payload, the logic arranging the segment plurality into a multiple-dimensional matrix;
• and
• a logic that analyzes segment data in a plurality of dimensions following passage of the data through a plurality of switches including analysis to detect segment error, column error, and payload error.

An interconnect structure comprising:

• a plurality of data switches arranged into a data switch stack;
• at least one input controller that submits requests to send a data packet through the data switch stack to a targeted output controller, the at least one input controller that detects and/or corrects errors utilizing communicated error correction bits;
• and
• at least one request processor that receives requests from the at least one input controller and governs data flow through the data switch stack to the output controller targeted by the data packet, the at least one request processor producing an answer packet for communication to the requesting input controller and formatting the answer packet with error correction bits for usage by the input controller for detecting and/or correcting errors.