Hardware assist system and method for the timing of packets in a wireless network
AssigneeCisco Technology, Inc.
InventorJohn Stratigakis
Life of this patent
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Abstract
In a wireless local area network (“WLAN”), a system and method for assisting the timing calculation associated with the transmission timing of packets or data frames through the air. The present utilizes the baseband PHY processor to detect the trailing edge of the radio frequency (“RF”) packet and prevents the WLAN device from transmitting for a pre-determined amount of time. This improved system and method thereby frees the medium access controller (“MAC”) from utilizing significant microprocessor cycles for synchronization calculations and thereby increases system throughput and reduces the possibility of fast-turnaround protocol timing errors.
Claims15
An apparatus, comprising:
- a receiver operable to receive a wireless signal;
- a transmitter operable to transmit a wireless signal;
- a detection circuit operable to detect when receiving of the wireless signal is completed coupled to the receiver;
- and
- a delay circuit configured to receive a signal to operate the transmitter and a signal from the detection circuit indicative of when receiving of the wireless signal is completed, the delay circuit comprises an output coupled to the transmitter;
- wherein the delay circuit is responsive to the signal from the detection circuit to delay passing the signal to operate the transmitter to the output coupled to the transmitter a predetermined time delay after the detection circuit detects receiving of the wireless signal is completed.
An apparatus, comprising:
- a wireless transmitter;
- a wireless receiver;
- a physical layer (PHY) processor coupled to the receiver and responsive to receive a first data packet from the wireless receiver, the PHY is also coupled to the transmitter and operable to send a second data packet to the transmitter for wireless transmission;
- a media access control (MAC) processor in data communication with the PHY processor;
- and
- a delay circuit coupled between the MAC processor and the PHY processor;
- wherein the PHY processor is configured to signal the delay circuit when receiving of the first packet is completed;
- wherein the MAC processor is operable to determine whether to send a response for the first packet;
- wherein the MAC processor is operable to generate the second packet responsive to determining to send a response to the first packet;
- wherein the MAC processor forwards the second packet to the PHY processor and signals the delay circuit to transmit the second packet;
- and
- wherein the PHY processor waits for a signal from the delay circuit before sending the second data packet to the transmitter for wireless transmission.
Dependencies are inferred from the claim text.