US 7,397,726 B1 · Flexible RAM clock enable

Abstract

A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. The first set of configuration logic is also configurable to provide a first port core clock signal for controlling the memory block core. The first port core clock signal can either be the same as the first port input clock signal, or can be controlled independently from the first port input clock signal. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block. The second set of configuration logic is also configurable to provide a second port core clock signal for controlling the memory block core. The second port core clock signal can be controlled independently from the second port input clock signal.

Claims21

Dependent claims

Clock configuration logic for a memory block of a programmable logic device, comprising:

a first set of clock configuration logic configurable to provide a first port input clock signal for controlling input registers of a first port of the memory block, the first set of clock configuration logic also configurable to provide a first port core clock signal for controlling a core of the memory block, wherein the first port core clock signal is the same as the first port input clock signal;
and
a second set of clock configuration logic configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block, the second set of clock configuration logic also configurable to provide a second port core clock signal for controlling the core of the memory block, wherein the second port core clock signal can be controlled independently from the second port input clock signal.

Clock configuration logic for a memory block of a programmable logic device, comprising:

a first set of clock configuration logic configurable to provide a first port input clock signal for controlling input registers of a first port of the memory block, the first set of clock configuration logic also configurable to provide a first port core clock signal for controlling a core of the memory block, wherein the first port core clock signal can be controlled independently from the first port input clock signal;
and
a second set of clock configuration logic configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block, the second set of clock configuration logic also configurable to provide a second port core clock signal for controlling the core of the memory block, wherein the second port core clock signal can be controlled independently from the second port input clock signal.

A method for configuring clock signals to control a memory block in a programmable logic device, comprising:

selecting a first port input clock signal from a group consisting of a first clock signal, the first clock signal tied to a first clock enable signal, and the first clock signal tied to a second clock enable signal;
selecting a first port core clock signal from a group consisting of the first clock signal, the first clock signal tied to the first clock enable signal, and the first clock signal tied to the second clock enable signal;
selecting a second port input clock signal from a group consisting of a second clock signal, the second clock signal tied to a third clock enable signal, the second clock signal tied to a fourth clock enable signal, and the first port input clock signal;
and
selecting a second port core clock signal from a group consisting of the second clock signal, the second clock signal tied to the third clock enable signal, the second clock signal tied to the fourth clock enable signal, and the first port core clock signal.

2 more elements

Dependencies are inferred from the claim text.

Flexible RAM clock enable

Life of this patent

Flexible RAM clock enable

Life of this patent

Abstract

Claims21