US 7,397,723 B2 · Fast read port for register file

Abstract

Separate read and write ports in a memory system allow simultaneous access to a memory cell array by read and write operations. A single cycle operation of a central processing unit coupled to a memory array depends on a memory access capability providing simultaneous reading and writing to different locations. A pair of pull-down transistor stacks connected to memory cell latch loops allows a single selected pull-down stack of the pair to toggle a memory cell latch loop to a desired data content without any requirement for a precharge scheme. A single pull-down stack of transistors connected to a memory cell latch loop provides a read port with low input loading. A sense amplifier provides a mid-supply-level precharging capability provided by a feedback device within a front-end inversion stage. When not in a feedback mode, the front-end inversion stage cascaded with a second inversion stage provides a rapid read response.

Claims14

Dependent claims

A method of reading a memory cell in a memory system, the method comprising:

receiving a read address of the memory cell;
applying a precharge enable signal to an integral precharge sense circuit;
applying a read enable signal to a read bitline multiplexer;
precharging a read bitline to a level of about one-half of a voltage source level;
applying
a read word line selection signal to a read port;
and
reading memory cell data with the integral precharge sense circuit.

5 more elements

Dependencies are inferred from the claim text.

Fast read port for register file

Life of this patent

Fast read port for register file

Life of this patent

Abstract

Claims14