Multiple block memory with complementary data path

A method of operating a memory having a data bus, a first memory block, a second memory block, a first sense amplifier coupled to the first memory block, a second sense amplifier coupled to the second memory block, a first circuit coupled between the first sense amplifier and the data bus, and a second circuit coupled between the second sense amplifier and the data bus, comprising:

• precharging the data bus through the first and second circuit;
• selecting the first memory block and deselecting the second memory block in response to a clock signal;
• terminating precharging the data bus through second circuit while maintaining precharging of the data bus through first circuit;
• and
• providing data from the first memory block to the data bus through the first circuit and terminating precharging of the data bus through the first circuit in response to a first sense enable signal.

A memory, comprising:

• a first memory block enabled in response to a first block select signal and having complementary outputs;
• a second memory block enabled in response to a second block select signal and having complementary outputs;
• a data bus having a true line and a complementary line;
• a first sense amplifier coupled to the complementary outputs of the first memory block, having a clock input responsive to a first sense enable signal, and having complementary outputs;
• a second sense amplifier coupled to complementary outputs of the second memory block, having a clock input responsive to a second sense enable signal, and having complementary outputs;
• a first tri-driver coupled to the complementary outputs of the first sense amplifier, having a clock input responsive to the first sense enable signal, and having complementary outputs coupled to the data bus, wherein the first tri-driver performs a function selected from the group consisting of precharging the data bus, providing a high impedance to the data bus, and providing complementary data on the data bus;
• and
• a second tri-driver coupled to the complementary outputs of the second sense amplifier, having a clock input responsive to the second sense enable signal, and having complementary outputs coupled to the data bus, wherein the second tri-driver performs a function selected from the group consisting of precharging the data bus, providing a high impedance to the data bus, and providing complementary data on the data bus.