Standby leakage current reduction circuit and semiconductor memory device comprising the standby leakage current reduction circuit

A circuit adapted to reduce a standby leakage current in a semiconductor memory device comprising memory cells, the circuit comprising:

• a temperature information generator;
• a bias signal generator electrically connected to the temperature information generator and adapted to generate a bias signal, wherein a voltage level of the bias signal is set in accordance with a temperature sensing signal output by the temperature information generator;
• and,
• a ground voltage controller connected between a ground terminal and a virtual ground terminal of at least one of the memory cells, adapted to receive the bias signal from the bias signal generator, and adapted to control a level of a voltage apparent on the virtual ground terminal in response to the bias signal while the semiconductor memory device is in a standby mode.

A semiconductor memory device comprising:

• a plurality of memory cells;
• a temperature information generator;
• a bias signal generator adapted to generate a bias signal and adapted to set a voltage level of the bias signal in accordance with a temperature sensing signal received from the temperature information generator and a result of a standby leakage current test;
• and,
• a ground voltage controller connected between a ground terminal and a virtual ground terminal of at least one of the memory cells, adapted to receive the bias signal from the bias signal generator, and adapted to control a level of a voltage apparent on the virtual ground terminal in response to the bias signal while the semiconductor memory device is in a standby mode.