Volatile semiconductor memory

A volatile semiconductor memory to perform self-test for detecting a defect of a memory cell, comprising:

• a refresh counter generating a row address and a column address to designate a memory cell where data is to be written or read when executing the self-test, and generates a refresh address to designate a row of a memory cell to be refreshed when performing refresh operation for holding data;
• a self-test controller detecting a defect of a memory cell;
• an address storage for storing a defective address indicating an address of a defective memory cell;
• and
• a refresh adjust circuit setting a refresh cycle of a memory cell designated by the defective address to be shorter than a refresh cycle of a normal memory cell.

A volatile semiconductor memory comprising:

• a memory cell array which has a plurality of cells;
• a self-test controller comparing a first data to be written into a selected cell of the cells and a second data actually read from the selected cell of the cells and outputting a comparison result;
• and
• a refresh controller controlling a refresh cycle of the selected cell in response to the comparison result.