Serial peripheral interface memory device with an accelerated parallel mode
AssigneeMacronix International Co., Ltd.
InventorsHan-Sung Chen, Chia-Yen Yeh, Chen-Hao Po, Ching-Chung Lin
Life of this patent
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Abstract
A serial peripheral flash memory device uses a plurality of dummy input/output terminals to enable the selection of a parallel mode for devices that have a slower serial clock speed. In parallel mode, data is transmitted over the plurality of dummy input/output terminals to allow a plurality of bits to be transmitted at the same time improving the data transmission rate at the slower serial clock speed.
Claims12
A method of operating a serial peripheral interface flash memory device, comprising:
- applying a parallel mode command to a first pin operatively coupled to an input/output interface of the memory device to cause the device to operate in a parallel data transmission mode;
- applying a chip select signal to a second pin of the memory device to enable operation in response to the parallel mode command;
- applying a serial clock signal to a third pin of the memory device;
- applying one of a read command and a write command to the first pin;
- and
- transmitting data in parallel on a fourth pin and additional pins, operatively coupled to the input/output interface, at a frequency corresponding to the serial clock signal, wherein data is transmitted only on the fourth pin and at the frequency when the device operates in a serial mode.
A semiconductor memory device comprising:
- an input/output interface;
- a serial data transmission input terminal, operably coupled to the input/output interface, for receiving a parallel mode command;
- a clock signal input terminal for receiving a serial clock signal;
- a serial data transmission terminal, operably coupled to the input/output interface, for serving as a sole data transmission pin in a serial mode for serially transmitting data at a frequency determined by the serial clock signal;
- a chip select input terminal for receiving a chip select signal to enable operation in response to the parallel mode command;
- a plurality of dummy input/output terminals, operably connected in parallel to the input/output interface, for transmitting data in the parallel mode in parallel with data being transmitted on the serial data transmission terminal at the frequency determined by the serial clock signal.
A serial peripheral interface flash memory integrated circuit device comprising:
- a serial data transmission input terminal, for receiving a data or command input;
- a clock signal input terminal for receiving a serial clock signal;
- a serial data transmission terminal, for serving as a sole data transmission pin in a serial mode for serially transmitting data at a frequency determined by the serial clock signal;
- a chip select input terminal for receiving a chip select signal;
- at least one voltage input terminal for receiving an applied voltage;
- a ground terminal for grounding the device;
- and
- a plurality of dummy input/output terminals for transmitting data in a parallel mode in parallel with data being transmitted on the serial data transmission terminal at the frequency determined by the serial clock signal.
Dependencies are inferred from the claim text.